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PDF IDT70825 Data sheet ( Hoja de datos )
| Número de pieza | IDT70825 | |
| Descripción | HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM) | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de IDT70825 (archivo pdf) en la parte inferior de esta página. Total 21 Páginas | ||
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Integrated Device Technology, Inc.
HIGH-SPEED 8K x 16
SEQUENTIAL ACCESS
RANDOM ACCESS MEMORY (SARAM™)
IDT70825S/L
FEATURES:
• 8K x 16 Sequential Access Random Access Memory
(SARAM™)
- Sequential Access from one port and standard Random
Access from the other port
- Separate upper-byte and lower-byte control of the
Random Access Port
• High-speed operation
- 20ns tAA for random access port
- 20ns tCD for sequential port
- 25ns clock cycle time
• Architecture based on Dual-Port RAM cells
• Electrostatic discharge > 2001V, Class II
• Compatible with Intel BMIC and 82430 PCI Set
• Width and Depth Expandable
• Sequential side
- Address based flags for buffer control
- Pointer logic supports two internal buffers
• Battery backup operation—2V data retention
• TTL-compatible, single 5V (±10%) power supply
• Available in 80-pin TQFP and 84-pin PGA
• Military product compliant to MIL-STD-883.
• Industrial temperature range (–40°C to +85°C) is available,
tested to military electrical specifications.
DESCRIPTION:
The IDT70825 is a high-speed 8K x 16-bit Sequential
Access Random Access Memory (SARAM). The SARAM
offers a single-chip solution to buffer data sequentially on one
port, and be accessed randomly (asynchronously) through
the other port. The device has a Dual-Port RAM based
architecture with a standard SRAM interface for the random
(asynchronous) access port, and a clocked interface with
counter sequencing for the sequential (synchronous) access
port.
Fabricated using CMOS high-performance technology,
this memory device typically operates on less than 900mW of
power at maximum high-speed clock-to-data and Random
Access. An automatic power down feature, controlled by CE,
permits the on-chip circuitry of each port to enter a very low
standby power mode.
The IDT70825 is packaged in a 80-pin Thin Plastic Quad
Flatpack (TQFP) or 84-pin Ceramic Pin Grid Array (PGA).
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A0-12 13
R/
LSB
MSB
I/O0-15
Random
Access
Port
Controls
16
13
13
13
8K X 16
Memory
Array
DataL
DataR
AddrL
AddrR
13
13
Sequential
Access
Port
Controls
16
Reg.
13
16
RST
Pointer/
Counter
SCLK
1
2
SR/
SI/O0-15
Start Address for Buffer #1
End Address for Buffer #1
Start Address for Buffer #2
End Address for Buffer #2
Flow Control Buffer
Flag Status
13
COMPARATOR
1
2
3016 drw 01
The IDT logo is a registered trademark and SARAM is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.31
OCTOBER 1996
DSC-3016/6
1
1 page  
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE
AND SUPPLY VOLTAGE RANGE(1) (VCC = 5.0V ± 10%)
Symbol
Parameter
Test
Condition
Version
70825X20 70825X25 70825X35 70825X45
Com'l. Only Com'l. Only
Typ.(2) Max. Typ.(2)Max. Typ.(2) Max. Typ.(2) Max. Unit
ICC
ISB1
ISB2
Dynamic Operating
Current
CE = VIL, Outputs MIL. S — — — —
Open, SCE = VIL(5)
L— — — —
(Both Ports Active)
f = fMAX(3)
COM’L. S 180 380 170 360
L 180 330 170 310
Standby Current
SCE and CE > VIH(7) MIL. S —
—
—
—
(Both Ports - TTL Level CMD = VIH
L— — — —
Inputs)
f = fMAX(3)
COM’L. S 25 70 25 70
L 25 50 25 50
Standby Current
CE or SCE = VIH
MIL. S — — —
(One Port - TTL Level Active Port Outputs
L —— —
—
—
Input)
Open, f = fMAX(3)
COM’L. S 115 260 105 250
L 115 230 105 220
160 400 155 400 mA
160 340 155 340
160 340 155 340
160 290 155 290
20 85 16 85 mA
20 65 16 65
20 70 16 70
20 50 16 50
95 290 90 290 mA
95 250 90 250
95 240 90 240
95 210 90 210
ISB3
ISB4
Full Standby Current
(Both Ports - CMOS
Level Inputs)
Full Standby Current
(One Port - CMOS
Level Inputs)
Both Ports CE and MIL. S — — — —
SCE ≥ VCC - 0.2V(6,7)
L— — — —
VIN ≥ VCC - 0.2V or COM’L. S 1.0 15 1.0 15
VIN ≤ 0.2V, f = 0(4)
L 0.2 5 0.2 5
One Port CE or
MIL. S — — — —
SCE ≥ VCC - 0.2V(6)
L— — — —
Outputs Open
(Active port), f = fMAX(3) COM’L. S 110 240 100 230
VIN ≥ VCC - 0.2V or
VIN ≤ 0.2V
L 110 200 100 190
1.0 30 1.0 30 mA
0.2 10 0.2 10
1.0 15 1.0 15
0.2 5 0.2 5
90 260 85 260 mA
90 215 85 215
90 220 85 220
90 180 85 180
NOTES:
3016 tbl 08
1. "X" in part number indicates power rating (S or L).
2. VCC = 5V, Ta = +25°C; guaranteed by device characterization but not production tested.
3. At f = fMAX, address, control lines (except Output Enable), and SCLK are cycling at the maximum frequency read cycle of 1/tRC.
4. f = 0 means no address or control lines change.
5. SCE may transition, but is Low (SCE=VIL) when clocked in by SCLK.
6. SCE may be ≤ 0.2V, after it is clocked in, since SCLK=VIH must be clocked in prior to powerdown.
7. If one port is enabled (either CE or SCE = Low) then the other port is disabled (SCE or CE = High, respectively). CMOS High > Vcc - 0.2V and
Low < 0.2V, and TTL High = VIH and Low = VIL.
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L VERSION ONLY) (VLC < 0.2V, VHC > VCC - 0.2V)
Symbol
Parameter
Test Condition
Min.
Typ.(1)
VDR
VCC for Data Retention
VCC = 2V
2.0 —
ICCDR Data Retention Current
CE = VHC
MIL.
— 100
VIN = VHC or = VLC COM’L.
—
100
tCDR(3)
tR(3)
Chip Deselect to Data Retention Time
Operation Recovery Time
SCE = VHC(4) when SCLK=
CMD = VHC
0
tRC(2)
—
—
NOTES :
1. TA = +25°C, VCC = 2V; guaranteed by device characterization but not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed by device characterization, but is not production tested.
4. To initiate data retention, SCE = VIH must be clocked in.
Max.
—
4000
1500
—
—
Unit
V
µA
ns
ns
3016 tbl 09
6.31 5
5 Page 
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CASES 8 AND 9: (RESERVED)
Illegal operations. All outputs will be HIGH on the I/O bus during a READ.
RANDOM ACCESS PORT: AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (2,3)
IDT70825X20 IDT70825X25 IDT70825X35 IDT70825X45
Com'l. Only Com'l. Only
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time
20 — 25 — 35 — 45 — ns
tAA Address Access Time
— 20 — 25 — 35 — 45 ns
tACE
Chip Enable Access Time
— 20 — 25 — 35 — 45 ns
tBE Byte Enable Access Time
— 20 — 25 — 35 — 45 ns
tOE Output Enable Access Time
— 10 — 10 — 15 — 20 ns
tOH
tCLZ
Output Hold from Address Change
Chip Select Low-Z Time(1)
3 — 3 — 3 — 3 — ns
3 — 3 — 3 — 3 — ns
tBLZ
Byte Enable Low-Z Time(1)
3 — 3 — 3 — 3 — ns
tOLZ
Output Enable Low-Z Time(1)
2 — 2 — 2 — 2 — ns
tCHZ
Chip Select High-Z Time(1)
— 10 — 12 — 15 — 15 ns
tBHZ
tOHZ
Byte Enable High-Z Time(1)
Output Enable High-Z Time(1)
— 10 — 12 — 15 — 15 ns
— 9 — 11 — 15 — 15 ns
tPU Chip Select Power-Up Time
0 — 0 — 0 — 0 — ns
tPD Chip Select Power-Down Time
— 20 — 25 — 35 — 45 ns
NOTES:
3016 tbl 20
1. Transition measured at ±200mV from steady state. This parameter is guaranteed with the AC Test Load (Figure 2) by device characterization, but is not
production tested.
2. "X" in part number indicates power rating (S or L).
3. CMD access follows standard timing listed for both read and write accesses, ( CE = VIH when CMD = VIL ) or ( CMD = VIH when CE = VIL ).
RANDOM ACCESS PORT: AC ELECTRICAL CHARACTERISTICS
OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE (2,4)
Symbol
Parameter
WRITE CYCLE
tWC Write Cycle Time
tCW Chip Select to End-of-Write
tAW Address Valid to End-of-Write(3)
tAS Address Set-up Time
tWP Write Pulse Width(3)
tBP Byte Enable Pulse Width(3)
tWR Write Recovery Time
tWHZ
Write Enable Output High-Z Time(1)
tDW Data Set-up Time
tDH Data Hold Time
tOW Output Active from End-of-Write
IDT70825X20
Com'l. Only
Min. Max.
IDT70825X25
Com'l. Only
Min. Max.
IDT70825X35 IDT70825X45
Min. Max. Min. Max. Unit
20 — 25 —
15 — 20 —
15 — 20 —
0—0—
13 — 20 —
15 — 20 —
0—0—
— 10 — 12
13 — 15 —
0—0—
3—3—
35 — 45 — ns
25 — 30 — ns
25 — 30 — ns
0 — 0 — ns
25 — 30 — ns
25 — 30 — ns
0 — 0 — ns
— 15 — 15 ns
20 — 25 — ns
0 — 0 — ns
3 — 3 — ns
NOTES:
3016 tbl 21
1. Transition measured at ±200mV from steady state. This parameter is guaranteed with the AC Test Load (Figure 2) by device characterization, but is not
production tested.
2. "X" in part number indicates power rating (S or L).
3. OE is continuously HIGH, OE = VIH. If during the R/W controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O
drivers to turn off and on the data to be placed on the bus for the required tDW. If OE is HIGH during the R/W controlled write cycle, this requirement does
not apply and the minimum write pulse is the specified tWP. For the CE controlled write cycle, OE may be LOW with no degradation to tCW timing.
4. CMD access follows standard timing listed for both read and write accesses, ( CE = VIH when CMD = VIL ) or ( CMD = VIH when CE = VIL ).
6.31 11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet IDT70825.PDF ] | |
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