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Integrated Device Technology - HIGH-SPEED 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS

Numéro de référence IDT707288L25G
Description HIGH-SPEED 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS
Fabricant Integrated Device Technology 
Logo Integrated Device Technology 





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IDT707288L25G fiche technique
Integrated Device Technology, Inc.
HIGH-SPEED
64K x 16 BANK-SWITCHABLE
DUAL-PORTED SRAM WITH
EXTERNAL BANK SELECTS
ADVANCED
IDT707288S/L
FEATURES:
• 64K x 16 Bank-Switchable Dual-Ported SRAM Architecture
- Four independent 16K x 16 banks
- 1 Megabit of memory on chip
• Fast asynchronous address-to-data access time: 20ns
• User-controlled input pins included for bank selects
• Independent port controls with asynchronous address &
data busses
• Four 16-bit mailboxes available to each port for inter-
processor communications; interrupt option
• Interrupt flags with programmable masking
• Dual Chip Enables allow for depth expansion without
external logic
UB and LB are available for bus matching to x8 or x16
busses; also support very fast banking
• TTL-compatible, single 5V (±10%) power supply
• Available in a 100-pin Thin Quad Plastic Flatpack (TQFP)
and a 108-pin ceramic Pin Grid Array (PGA)
DESCRIPTION:
The IDT707288 is a high-speed 64K x 16 (1M bit) Bank-
Switchable Dual-Ported SRAM organized into four indepen-
dent 16K x 16 banks. The device has two independent ports
with separate controls, addresses, and I/O pins for each port,
allowing each port to asynchronously access any 16K x 16
memory block not already accessed by the other port. Ac-
cesses by the ports into specific banks are controlled via bank
select pin inputs under the user's control. Mailboxes are
provided to allow inter-processor communications. Interrupts
are provided to indicate mailbox writes have occurred. An
automatic power down feature controlled by the chip enables
(CE0 and CE1) permits the on-chip circuitry of each port to
enter a very low standby power mode and allows fast depth
expansion.
The IDT707288 offers a maximum address-to-data access
time as fast as 20ns, while typically operating on only 900mW
of power, and is available in a 100-pin Thin Quad Plastic
Flatpack (TQFP) and a 108-pin ceramic Pin Grid Array (PGA).
FUNCTIONAL BLOCK DIAGRAM
R/ L
0L
CE1L
L
L
L
CONTROL
LOGIC
MUX
16Kx16
MEMORY
ARRAY
(BANK 0)
MUX
CONTROL
LOGIC
R/ R
0R
CE1R
R
R
R
I/O8L-15L
I/O0L-7L
I/O
CONTROL
A13L
A0L(1)
ADDRESS
DECODE
MUX
16Kx16
MEMORY
ARRAY
(BANK 1)
MUX
I/O
CONTROL
I/O8R-15R
I/O0R-7R
ADDRESS
DECODE
A13R
A0R(1)
BA1L
BA0L
BANK
DECODE
MUX
16Kx16
MEMORY
ARRAY
(BANK 3)
BANK
DECODE
BA1R
BA0R
MUX
BKSEL3(2)
BANK
BKSEL0(2)
SELECT
A5L(1)
A5R(1)
A0L(1)
MAILBOX
A0R(1)
L/ L
L
R/ L
INTERRUPT
LOGIC
R/
R
R/ R
R
NOTES:
L
L
LR
R
R
3592 drw 01
1. The first six address pins for each port serve dual functions. When MBSEL = VIH, the pins serve as memory address inputs. When MBSEL = VIL, the pins
serve as mailbox address inputs.
2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Table I for more details.
The IDT logo is a registered trademark of Integrated Device Technology
COMMERCIAL TEMPERATURE RANGE
OCTOBER 1996
©1996 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
6.29
DSC-3592/-
1

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