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Integrated Device Technology - HIGH-SPEED 4K x 18 DUAL-PORT STATIC RAM

Numéro de référence IDT7034S15PF
Description HIGH-SPEED 4K x 18 DUAL-PORT STATIC RAM
Fabricant Integrated Device Technology 
Logo Integrated Device Technology 





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IDT7034S15PF fiche technique
HIGH-SPEED
4K x 18 DUAL-PORT
STATIC RAM
IDT7034S/L
Features:
x True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
x High-speed access
— Commercial: 15/20ns (max.)
x Low-power operation
— IDT7034S
Active: 850mW (typ.)
Standby: 5mW (typ.)
— IDT7034L
Active: 850mW (typ.)
Standby: 1mW (typ.)
x Separate upper-byte and lower-byte control for multiplexed
bus compatibility
x IDT7034 easily expands data bus width to 36 bits or more
using the Master/Slave select when cascading more than
one device
x M/S = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
x Interrupt Flag
x On-chip port arbitration logic
x Full on-chip hardware support of semaphore signaling
between ports
x Fully asynchronous operation from either port
x Battery backup operation—2V data retention
x TTL-compatible, single 5V (±10%) power supply
x Available in 100-pin Thin Quad Flatpack
x Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/WL
UBL
R/WR
UBR
LBL
CEL
OEL
LBR
CER
OER
I/O9L-I/O17L
I/O0L-I/O8L
BUSYL(1,2)
I/O
Control
I/O
Control
A11L
A0L
Address
Decoder
13
CEL
OEL
R/WL
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
13
SEML
INTL(2)
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
M/S
Address
Decoder
CER
OER
R/WR
I/O9R-I/O17R
.
I/O0R-I/O8R
BUSYR(1,2)
A11R
A0R
SEMR
INTR(2)
4089 drw 01
©1999 Integrated Device Technology, Inc.
SEPTEMBER 1999
1
DSC 4089/6

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