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PDF IDT7024 Data sheet ( Hoja de datos )
| Número de pieza | IDT7024 | |
| Descripción | HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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Integrated Device Technology, Inc.
HIGH-SPEED
4K x 16 DUAL-PORT
STATIC RAM
IDT7024S/L
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Military: 20/25/35/55/70ns (max.)
— Commercial: 15/17/20/25/35/55ns (max.)
• Low-power operation
— IDT7024S
Active: 750mW (typ.)
Standby: 5mW (typ.)
— IDT7024L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• Separate upper-byte and lower-byte control for
multiplexed bus compatibility
• IDT7024 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading
more than one device
• M/S = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
• Busy and Interrupt Flags
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Devices are capable of withstanding greater than 2001V
electrostatic discharge.
• Fully asynchronous operation from either port
• Battery backup operation—2V data retention
• TTL-compatible, single 5V (±10%) power supply
• Available in 84-pin PGA, 84-pin quad flatpack, 84-pin
PLCC, and 100-pin Thin Quad Plastic Flatpack
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
FUNCTIONAL BLOCK DIAGRAM
R/WL
UBL
R/ WR
UBR
LBL LBR
CEL CER
OEL OER
I/O8L-I/O 15L
I/O0L-I/O 7L
BUSYL(1,2)
A11L
A0L
NOTES:
1. (MASTER):
BUSY is output;
(SLAVE): BUSY
is input.
2. BUSY outputs
and INT outputs
are non-tri-stated
push-pull.
SEML
INTL(2)
I/O
Control
I/O
Control
Address
Decoder
CEL
OEL
R/ WL
12
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/S
Address
Decoder
12
CER
OER
R/WR
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.15
I/O8R-I/O 15R
I/O0R-I/O 7R
BUSYR(1,2)
A11R
A0R
SEMR
INTR(2)
2740 drw 01
OCTOBER 1996
DSC-2740/6
1
1 page  
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%)
IDT7024S
IDT7024L
Symbol
|ILI|
Parameter
Input Leakage Current(1)
Test Conditions
VCC = 5.5V, VIN = 0V to VCC
Min.
—
Max.
10
Min.
—
Max.
5
|ILO| Output Leakage Current
CE = VIH, VOUT = 0V to VCC
— 10 — 5
VOL Output Low Voltage
IOL = 4mA
— 0.4 — 0.4
VOH Output High Voltage
IOH = -4mA
2.4 — 2.4 —
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
Unit
µA
µA
V
V
2740 tbl 08
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 5.0V ± 10%)
Symbol Parameter
ICC Dynamic Operating
Current
(Both Ports Active)
Test
Condition
CE"A"=VIL, Outputs Open
SEM = VIH
f = fMAX(3)
Version
MIL S
L
7024X15
Com'l. Only
Typ.(2) Max.
——
——
7024X17
Com'l. Only
Typ.(2) Max.
——
——
7024X20
Typ.(2) Max.
160 370
160 320
COM S 170 310 170 310 160 290
L 170 260 170 260 160 240
7024X25
Typ.(2)Max. Unit
155 340 mA
155 280
155 265
155 220
ISB1 Standby Current CER = CEL = VIH
(Both Ports — TTL SEMR = SEML = VIH
MIL S — — — — 20 90 16 80 mA
L — — — — 20 70 16 65
Level Inputs)
f = fMAX(3)
COM S 20 60 20 60 20 60 16 60
L 20 50 20 50 20 50 16 50
ISB2 Standby Current CE"A"=VIL and CE"B"=VIL(5) MIL S — — — — 95 240 90 215 mA
(One Port — TTL Active Port Outputs Open
L — — — — 95 210 90 180
Level Inputs)
f = fMAX(3)
COM S 105 190 105 190 95 180 90 170
SEMR = SEML = VIH
L 105 160 105 160 95 150 90 140
ISB3 Full Standby Current Both Ports CEL and
(Both Ports — All CER >VCC - 0.2V
MIL S — — — — 1.0 30 1.0 30 mA
L — — — — 0.2 10 0.2 10
CMOS Level Inputs) VIN > VCC - 0.2V or
COM S 1.0 15 1.0 15 1.0 15 1.0 15
VIN < 0.2V, f = 0(4)
L 0.2 5 0.2 5 0.2 5 0.2 5
SEMR = SEML> VCC - 0.2V
ISB4 Full Standby Current CE"A" < 0.2 and
MIL S — — — — 90 225 85 200 mA
(One Port — All
CE"B" > VCC - 0.2V (5)
L — — — — 90 200 85 170
CMOS Level Inputs) SEMR = SEML> VCC - 0.2V
VIN > VCC - 0.2V or
COM S 100 170 100 170 90 155 85 145
VIN < 0.2V, Active Port
L 100 140 100 140 90 130 85 120
Outputs Open,
f = fMAX(3)
NOTES:
2740 tbl 09
1. "X" in part numbers indicates power rating (S or L).
2. VCC = 5V, TA = +25°C, and are not production tested. ICC DC = 120mA (typ.)
3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.15 5
5 Page 
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
A0-A2
SEM
I/O0
R/W
VALID ADDRESS
tAW
tEW
tWR
tDW
DATAIN
VALID
tAS tWP
tDH
tSAA
VALID ADDRESS
tACE
tOH
tSOP
DATAOUT
VALID(2)
tSWRD
tAOE
OE
Write Cycle
Read Cycle
NOTES:
1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle).
2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.
2740 drw 11
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2) “A”
WR/ "A"
SEM"A"
A0"B"-A2"B"
SIDE(2) “B”
WR/ "B"
tSPS
MATCH
SEM"B"
2740 drw 12
NOTES:
1. D0R = D0L = VIL, CER = CEL = VIH, or both UB & LB = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/WA or SEMA going High to R/WB or SEMB going High.
4. If tSPS is not satisfied, there is no guarantee which side will be granted the Semaphore flag.
6.15 11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet IDT7024.PDF ] | |
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