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PDF IDT7007 Data sheet ( Hoja de datos )
| Número de pieza | IDT7007 | |
| Descripción | HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de IDT7007 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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Integrated Device Technology, Inc.
HIGH-SPEED
32K x 8 DUAL-PORT
STATIC RAM
IDT7007S/L
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Military: 25/35/55ns (max.)
— Commercial: 20/25/35/55ns (max.)
• Low-power operation
— IDT7007S
Active: 750mW (typ.)
Standby: 5mW (typ.)
— IDT7007L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• IDT7007 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading
more than one device
• M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
• Busy and Interrupt Flags
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than 2001V
electrostatic discharge
• TTL-compatible, single 5V (±10%) power supply
• Available in 68-pin PGA, 68-pin PLCC, and a 80-pin
TQFP
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
FUNCTIONAL BLOCK DIAGRAM
OEL
WCEL
R/ L
OER
CER
WR/ R
I/O0L- I/O7L
BUSYL(1,2)
A14L
A0L
I/O
Control
I/O
Control
Address
Decoder
CEL
OEL
WR/ L
15
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
15
CER
WOER
R/ R
I/O0R-I/O7R
BUSYR(1,2)
A14R
A0R
SEML
(2)
INTL
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
M/S
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.08
2940 drw 01
SEMR
(2)
INTR
OCTOBER 1996
DSC-2940/4
1
1 page  
IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE: NON-CONTENTION READ/WRITE CONTROL
Inputs(1)
Outputs
CE R/W OE SEM I/O0-7
Mode
H X X H High-Z Deselected: Power-Down
L
L
X H DATAIN
Write to Memory
L
H
L
H DATAOUT
Read Memory
X X H X High-Z Outputs Disabled
NOTE:
1. A0L — A14L ≠ A0R — A14R.
2940 tbl 02
TRUTH TABLE: SEMAPHORE READ/WRITE CONTROL(1)
Inputs
Outputs
CE R/W OE SEM I/O0-7
Mode
H
H
L
L DATAOUT
Read Semaphore Flag Data Out (I/O0-I/O7)
H X L DATAIN Write I/O0 into Semaphore Flag
L X XL —
Not Allowed
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0 - A2.
2940 tbl 03
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commercial Military Unit
VTERM(2)
Terminal Voltage –0.5 to +7.0
with Respect
to GND
–0.5 to +7.0
V
TA Operating
0 to +70 –55 to +125 °C
Temperature
TBIAS
Temperature
Under Bias
–55 to +125 –65 to +135 °C
TSTG
Storage
Temperature
–55 to +125 –65 to +150 °C
IOUT
DC Output
Current
50 50 mA
NOTES:
2940 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time
or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc
+ 0.5V.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Ambient
Temperature
GND
VCC
Military
–55°C to +125°C
0V 5.0V ± 10%
Commercial
0°C to +70°C
0V 5.0V ± 10%
2940 tbl 05
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Parameter
Min. Typ.
VCC Supply Voltage
4.5 5.0
GND Supply Voltage
00
VIH
Input High Voltage
2.2 —
VIL Input Low Voltage –0.5(1) —
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.5V.
Max. Unit
5.5 V
0V
6.0(2) V
0.8 V
2940 tbl 06
CAPACITANCE(1)
(TA = +25°C, f = 1.0MHz)TQFP ONLY
Symbol
Parameter
Conditions(1) Max.
CIN
Input Capacitance VIN = 3dV
9
COUT
Output
Capacitance
VOUT = 3dV
10
Unit
pF
pF
NOTES:
2940 tbl 07
1. This parameter is determined by device characterization but is not
production tested.
2. 3dV represents the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
6.08 5
5 Page 
IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1,5,8)
tWC
ADDRESS
(7)
tHZ
OE
CE or SEM(9)
tAW
R/W
DATAOUT
DATAIN
tAS(6)
(4)
tWP(2)
tWZ(7)
tDW
tWR(3)
tOW
tDH
(4)
2940 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE CONTROLLED TIMING(1,5)
ADDRESS
tWC
CE or SEM(9)
R/W
tAS(6)
tAW
tEW(2)
tWR(3)
tDW tDH
DATAIN
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
2940 drw 10
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured + 200mV from steady state with the Output
Test Load (Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
6.08 11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet IDT7007.PDF ] | |
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