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National Semiconductor - Hex D Flip-Flop with Master Reset

Numéro de référence 74F174
Description Hex D Flip-Flop with Master Reset
Fabricant National Semiconductor 
Logo National Semiconductor 





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74F174 fiche technique
November 1994
54F 74F174 Hex D Flip-Flop with Master Reset
General Description
The ’F174 is a high-speed hex D flip-flop The device is
used primarily as a 6-bit edge-triggered storage register
The information on the D inputs is transferred to storage
during the LOW-to-HIGH clock transition The device has a
Master Reset to simultaneously clear all flip-flops
Features
Y Edge-triggered D-type inputs
Y Buffered positive edge-triggered clock
Y Asynchronous common reset
Y Guaranteed 4000V minimum ESD protection
Commercial
74F174PC
74F174SC (Note 1)
74F174SJ (Note 1)
Military
54F174DM (Note 2)
54F174FM (Note 2)
54F174LM (Note 2)
Package
Number
N16E
J16A
M16A
M16D
W16A
E20A
Package Description
16-Lead (0 300 Wide) Molded Dual-In-Line
16-Lead Ceramic Dual-In-Line
16-Lead (0 150 Wide) Molded Small Outline JEDEC
16-Lead (0 300 Wide) Molded Small Outline EIAJ
16-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use Suffix e SCX and SJX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbols
Connection Diagrams
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9489–3
IEEE IEC
TL F 9489 – 1
TL F 9489 – 2
TL F 9489–5
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9489
RRD-B30M75 Printed in U S A

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