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PDF 74F164 Data sheet ( Hoja de datos )
| Número de pieza | 74F164 | |
| Descripción | 8-bit serial-in parallel-out shift register | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 74F164 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
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INTEGRATED CIRCUITS
74F164
8-bit serial-in parallel-out shift register
Product specification
IC15 Data Handbook
1995 Sep 22
Philips
Semiconductors
1 page  
Philips Semiconductors
8-bit serial-in parallel-out shift register
Product specification
74F164
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST
CONDITION
fmax Maximum clock frequency Waveform 1
tPLH Propagation delay
tPHL
CP to Qn
Waveform 1
tPHL
Propagation delay
MR to Qn
Waveform 3
Tamb = +25°C
VCC = 5V
CL = 50pF
RL = 500Ω
MIN TYP MAX
80 100
3.0 5.0 8.0
5.0 7.0 10.0
5.5 7.5 10.5
LIMITS
Tamb = 0°C to +70°C
VCC = +5V±10%
CL = 50pF
RL = 500Ω
MIN MAX
80
2.5 9.0
5.0 11.0
5.5 11.5
Tamb = –40°C to +85°C
VCC = +5V±10%
CL = 50pF
RL = 500Ω
UNIT
MIN MAX
80 MHz
2.5
5.0
9.0
11.0
ns
5.5 11.5 ns
AC SETUP REQUIREMENTS
SYMBOL
PARAMETER
ts(H)
tS(L)
th(H)
th(L)
tw(H)
tw(L)
tw(L)
tREC
Setup time, High or Low
Dn to CP
Hold time, High or Low
Dn to CP
CP Pulse width
High or Low
MR Pulse wicth
Low
Recovery time
MR to CP
TEST
CONDITION
Waveform 2
Waveform 2
Waveform 1
Waveform 3
Tamb = +25°C
VCC = 5V
CL = 50pF
RL = 500Ω
MIN TYP MAX
7.0
7.0
1.0
1.0
4.0
7.0
7.0
LIMITS
Tamb = 0°C to +70°C
VCC = +5V±10%
CL = 50pF
RL = 500Ω
MIN MAX
7.0
7.0
2.0
2.0
4.0
7.0
7.0
Tamb = –40°C to +85°C
VCC = +5V±10%
CL = 50pF
RL = 500Ω
UNIT
MIN MAX
7.0
7.0
ns
2.0
2.0
ns
4.0
7.0
ns
7.0 ns
Waveform 3 7.0
7.0 7.0 ns
AC WAVEFORMS
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
CP VM
1/fmax
tw(H)
tPHL
VM
tw(L)
VM
tPLH
MR VM
tw(L)
CP
VM
tREC
VM
Qn VM
VM
SF00294
Waveform 1. Propagation delay for Clock input to output,
Clock Pulse width, and maximum Clock frequency
tPHL
Qn VM
SF00158
Waveform 3. Master Reset pulse width, Master Reset to output
delay and Master Reset to Clock recovery time
Dn VM VM
ts(H) th(H)
VM VM
ts(L) th(L)
CP VM
VM
Waveform 2. Data setup and hold times
SF00191
1995 Sep 22
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74F164.PDF ] | |
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