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PDF 74ALVCR162601 Data sheet ( Hoja de datos )
| Número de pieza | 74ALVCR162601 | |
| Descripción | Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in the Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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September 2001
Revised October 2001
74ALVCR162601
Low Voltage 18-Bit Universal Bus Transceivers
with 3.6V Tolerant Inputs and Outputs
and 26Ω Series Resistors in the Outputs
General Description
The 74ALVCR162601, 18-bit universal bus transceiver,
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. The clock can be con-
trolled by the clock-enable (CLKENAB and CLKENBA)
inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When LEAB is
LOW, the A data is latched if CLKAB is held at a HIGH-to-
LOW logic level. If LEAB is LOW, the A bus data is stored
in the latch/flip-flop on the LOW-to-HIGH transition of
CLKAB. Output-enable OEAB is active-LOW. When OEAB
is HIGH, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, CLKBA and CLKENBA.
The 74ALVCR162601 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The 74ALVCR162601 is also designed with 26Ω series
resistors on both the A and B Port outputs. This design
reduces line noise in applications such as memory address
drivers, clock drivers, and bus transceivers/transmitters.
Features
I 1.65–3.6V VCC supply operation
I 3.6V tolerant inputs and outputs
I 26Ω series resistors on both the A and B Port outputs.
I tPD (A to B, B to A)
4.3 ns max for 3.0V to 3.6V VCC
5.1 ns max for 2.3V to 2.7V VCC
9.2 ns max for 1.65V to 1.95V VCC
I Power-down HIGH impedance inputs and outputs
I Supports live insertion/withdrawal (Note 1)
I Uses patented noise/EMI reduction circuitry
I Latchup conforms to JEDEC JED78
I ESD performance:
Human body model > 2000V
Machine model >200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
Package
Number
Package Description
74ALVCR162601T
MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2001 Fairchild Semiconductor Corporation DS500660
www.fairchildsemi.com
1 page  
AC Loading and Waveforms
Table 1: Values for Figure 1
TEST
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
SWITCH
Open
VL
GND
FIGURE 1. AC Test Circuit
Symbol
Vmi
Vmo
VX
VY
VL
Table 2: Variable Matrix
( Input Charactertistics: f = 1MHz; tr=tf=2ns; Z0= 50Ω )
3.3V ± 0.3V
2.7V
VCC
2.5V ± 0.2V
1.5V
1.5V
VOL + 0.3V
VOH − 0.3V
6V
1.5V
1.5V
VOL + 0.3V
VOH − 0.3V
6V
VCC/2
VCC/2
VOL + 0.15V
VOH − 0.15V
VCC*2
1.8V ± 0.15V
VCC/2
VCC/2
VOL + 0.15V
VOH − 0.15V
VCC*2
FIGURE 2. Waveform for Inverting
and Non-inverting Functions
FIGURE 4. 3-STATE Output Low Enable
and Disable Times for Low Voltage Logic
FIGURE 3. 3-STATE Output High Enable
and Disable Times for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width
and trec Waveforms
FIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet 74ALVCR162601.PDF ] | |
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