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PDF 74ALVCH245 Data sheet ( Hoja de datos )
| Número de pieza | 74ALVCH245 | |
| Descripción | Low Voltage Bidirectional Transceiver with Bushold | |
| Fabricantes | Fairchild Semiconductor | |
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September 2001
Revised February 2002
74ALVCH245
Low Voltage Bidirectional Transceiver with Bushold
General Description
The ALVCH245 contains eight non-inverting bidirectional
buffers with 3-STATE outputs and is intended for bus ori-
ented applications. The T/R input determines the direction
of data flow. The OE input disables both the A and B Ports
by placing them in a high impedance state. The ALVCH245
data inputs include active bushold circuitry, eliminating the
need for external pull-up resistors to hold unused or float-
ing data inputs at a valid logic level.
The 74ALVCH245 is designed for low voltage (1.65V to
3.6V) VCC applications.
The 74ALVCH245 is fabricated with an advanced CMOS
technology to achieve high-speed operation while main-
taining low CMOS power dissipation.
Features
s 1.65V to 3.6V VCC supply operation
s Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
s tPD
3.6 ns max for 3.0V to 3.6V VCC
4.2 ns max for 2.3V to 2.7V VCC
6 ns max for 1.65V to 1.95V VCC
s Uses patented Quiet Series noise/EMI reduction
circuitry
s Latchup conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model > 200V
Ordering Code:
Order Number Package Number
Package Description
74ALVCH245WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ALVCH245MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Description
OE
T/R
A0–A7
B0–B7
Output Enable Input (Active LOW)
Transmit/Receive Input
Side A Bushold Inputs or 3-STATE Outputs
Side B Bushold Inputs or 3-STATE Outputs
Quiet Series is a trademark of Fairchild Semiconductor Corporation.
© 2002 Fairchild Semiconductor Corporation DS500648
www.fairchildsemi.com
1 page  
AC Loading and Waveforms
TABLE 1. Values for Figure 1
TEST
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
SWITCH
Open
VL
GND
FIGURE 1. AC Test Circuit
TABLE 2. Variable Matrix
(Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 = 50Ω)
Symbol
Vmi
Vmo
Vx
Vy
VL
3.3V ± 0.3V
1.5V
1.5V
VOL + 0.3V
VOH − 0.3V
6V
VCC
2.7V
2.5V ± 0.2V
1.5V
1.5V
VOL + 0.3V
VOH − 0.3V
6V
VCC/2
VCC/2
VOL + 0.15V
VOH − 0.15V
VCC*2
1.8V ± 0.15V
VCC/2
VCC/2
VOL + 0.15V
VOH − 0.15V
VCC*2
FIGURE 2. Waveform for Inverting and Non-inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
5 www.fairchildsemi.com
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74ALVCH245.PDF ] | |
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