PDF 74ALVCH162374T Data sheet ( Hoja de datos )

Número de pieza	74ALVCH162374T
Descripción	Low Voltage 16-Bit D-Type Flip-Flop with Bushold and 26 Series Resistors in Outputs
Fabricantes	Fairchild Semiconductor
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No Preview Available ! September 2001 Revised February 2002 74ALVCH162374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold and 26Ω Series Resistors in Outputs General Description The ALVCH162374 contains sixteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus ori- ented applications. The device is byte controlled. A buff- ered clock (CP) and output enable (OE) are common to each byte and can be shorted together for full 16-bit opera- tion. The ALVCH162374 data inputs include active bushold cir- cuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. The 74ALVCH162374 is also designed with 26Ω series resistors in the outputs. This design reduces line noise in applications such as memory address drivers, clock drivers and bus transceivers/transmitters. The 74ALVCH162374 is designed for low voltage (1.65V to 3.6V) VCC applications with output compatibility up to 3.6V. The 74ALVCH162374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. Features s 1.65V to 3.6V VCC supply operation s 3.6V tolerant control inputs and outputs s Bushold data inputs eliminates the need for external pull-up/pull-down resistors s 26Ω series resistors in outputs s tPD (CLK to On) 4.6 ns max for 3.0V to 3.6V VCC 5.4 ns max for 2.3V to 2.7V VCC 9.6 ns max for 1.65V to 1.95V VCC s Uses patented noise/EMI reduction circuitry s Latch-up conforms to JEDEC JED78 s ESD performance: Human body model > 2000V Machine model > 200V Ordering Code: Order Number Package Number Package Descriptions 74ALVCH162374T MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names OEn CPn I0–I15 O0–O15 Description Output Enable Input (Active LOW) Clock Pulse Input Bushold Inputs Outputs © 2002 Fairchild Semiconductor Corporation DS500628 www.fairchildsemi.com 1 page AC Loading and Waveforms TABLE 1. Values for Figure 1 TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ SWITCH Open VL GND FIGURE 1. AC Test Circuit TABLE 2. Variable Matrix (Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 = 50Ω) Symbol Vmi Vmo VX VY VL 3.3V ± 0.3V 1.5V 1.5V VOL + 0.3V VOH − 0.3V 6V VCC 2.7V 2.5V ± 0.2V 1.5V 1.5V VOL + 0.3V VOH − 0.3V 6V VCC/2 VCC/2 VOL + 0.15V VOH − 0.15V VCC2 1.8V ± 0.15V VCC/2 VCC/2 VOL + 0.15V VOH − 0.15V VCC2 FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic FIGURE 5. Propagation Delay, Pulse Width and tREC Waveforms FIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic 5 www.fairchildsemi.com 5 Page

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