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PDF 74ALVC162827 Data sheet ( Hoja de datos )
| Número de pieza | 74ALVC162827 | |
| Descripción | Low Voltage 20-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in the Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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November 2001
Revised November 2001
74ALVC162827
Low Voltage 20-Bit Buffer/Line Driver
with 3.6V Tolerant Inputs and Outputs
and 26Ω Series Resistors in the Outputs
General Description
The ALVC162827 contains twenty non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is byte controlled. Each byte has NOR
output enables for maximum control flexibility.
The 74ALVC162827 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O capability up to 3.6V. The
ALVC162827 is also designed with 26Ω resistors in the
outputs.
The 74ALVC162827 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.65V to 3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s 26Ω series resistors in outputs
s tPD
3.9 ns max for 3.0V to 3.6V VCC
4.6 ns max for 2.3V to 2.7V VCC
8.2 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal (Note 1)
s Uses patented noise/EMI reduction circuitry
s Latchup conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74ALVC162827T
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OEn
I0–I19
O0–O19
Description
Output Enable Input (Active LOW)
Inputs
Outputs
© 2001 Fairchild Semiconductor Corporation DS500698
www.fairchildsemi.com
1 page  
AC Loading and Waveforms
TABLE 1. Values for Figure 1
TEST
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
SWITCH
Open
VL
GND
FIGURE 1. AC Test Circuit
TABLE 2. Variable Matrix
(Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 =50Ω
Symbol
Vmi
Vmo
VX
VY
VL
3.3V ± 0.3V
1.5V
1.5V
VOL + 0.3V
VOH − 0.3V
6V
2.7V
1.5V
1.5V
VOL + 0.3V
VOH − 0.3V
6V
VCC
2.5V ± 0.2V
VCC/2
VCC/2
VOL + 0.15V
VOH − 0.15V
VCC*2
1.8V ± 0.15V
VCC/2
VCC/2
VOL + 0.15V
VOH − 0.15V
VCC*2
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
5 www.fairchildsemi.com
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| Páginas | Total 6 Páginas | |
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| 74ALVC162827 | Low Voltage 20-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in the Outputs | Fairchild Semiconductor |
| 74ALVC162827T | Low Voltage 20-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in the Outputs | Fairchild Semiconductor |
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