|
|
PDF 74ALVC16244MTD Data sheet ( Hoja de datos )
| Número de pieza | 74ALVC16244MTD | |
| Descripción | Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 74ALVC16244MTD (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
|
No Preview Available !
October 2001
Revised October 2001
74ALVC16244
Low Voltage 16-Bit Buffer/Line Driver
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16244 contains sixteen non-inverting buffers with
3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The 74ALVC16244 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O capability up to 3.6V.
The 74ALVC16244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.65V–3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s tPD
3.0 ns max for 3.0V to 3.6V VCC
3.5 ns max for 2.3V to 2.7V VCC
6.0 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal (Note 1)
s Uses patented noise/EMI reduction circuitry
s Latch-up conforms to JEDEC JED98
s ESD performance:
Human body model > 2000V
Machine model > 200V
s Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74ALVC16244GX
(Note 2)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
74ALVC16244MTD
(Note 3)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: BGA package available in Tape and Reel only.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation DS500677
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
Symbol
Parameter
tPHL, tPLH
tPZL, tPZH
tPLZ, tPHZ
Propagation Delay
Output Enable Time
Output Disable Time
TA = −40°C to +85°C, RL = 500Ω
CL = 50 pF
CL = 30 pF
VCC = 3.3V ± 0.3V
VCC = 2.7V
VCC = 2.5V ± 0.2V VCC = 1.8V ± 0.15V
Min Max Min Max Min Max Min Max
1.3 3 1.5 3.5 1.0 3.0 1.5 6.0
1.3 4.0 1.5 4.6 1.0 4.1 1.5 8.2
1.3 4.0 1.5 4.3 1.0 3.8 1.5 6.8
Units
ns
ns
ns
Capacitance
Symbol
Parameter
Conditions
CIN
COUT
CPD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Outputs Enabled
VI = 0V or VCC
VI = 0V or VCC
f = 10 MHz, CL = 0 pF
TA = +25°C
VCC Typical
3.3 6
3.3 7
3.3 20
2.5 20
Units
pF
pF
pF
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 74ALVC16244MTD.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 74ALVC16244MTD | Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs | Fairchild Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |