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PDF 74AHCT74 Data sheet ( Hoja de datos )
| Número de pieza | 74AHCT74 | |
| Descripción | Dual D-type flip-flop with set and reset; positive-edge trigger | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
74AHC74; 74AHCT74
Dual D-type flip-flop with set and
reset; positive-edge trigger
Product specification
Supersedes data of 1999 Aug 05
File under Integrated Circuits, IC06
1999 Sep 23
1 page  
Philips Semiconductors
Dual D-type flip-flop with set and reset;
positive-edge trigger
Product specification
74AHC74; 74AHCT74
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
VCC
VI
VO
Tamb
DC supply voltage
input voltage
output voltage
operating ambient temperature
tr,tf (∆t/∆f) input rise and fall rates
CONDITIONS
74AHC
74AHCT
UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
2.0 5.0 5.5 4.5 5.0 5.5 V
0 − 5.5 0 − 5.5 V
0 − VCC 0 − VCC V
see DC and AC −40 +25 +85 −40 +25 +85 °C
characteristics per −40 +25 +125 −40 +25 +125 °C
device
VCC = 3.3 V ±0.3 V − − 100 − − − ns/V
VCC = 5 V ±0.5 V − − 20 − − 20
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
CONDITIONS
VCC DC supply voltage
VI input voltage
IIK DC input diode current
VI < −0.5 V; note 1
IOK DC output diode current
VO < −0.5 V or VO > VCC + 0.5 V; note 1
IO DC output source or sink current −0.5 V < VO < VCC + 0.5 V
ICC DC VCC or GND current
Tstg storage temperature
PD power dissipation per package for temperature range: −40 to +85 °C; note 2
MIN. MAX. UNIT
−0.5 +7.0 V
−0.5 +7.0 V
− −20 mA
− ±20 mA
− ±25 mA
− ±75 mA
−65 +150 °C
− 500 mW
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO packages: above 70 °C the value of PD derates linearly with 8 mW/K.
For TSSOP packages: above 60 °C the value of PD derates linearly with 5.5 mW/K.
1999 Sep 23
5
5 Page 
Philips Semiconductors
Dual D-type flip-flop with set and reset;
positive-edge trigger
AC WAVEFORMS
Product specification
74AHC74; 74AHCT74
handbook, full pagewidth
VI
nD INPUT
GND
VI
nCP INPUT
GND
VOH
nQ OUTPUT
VOL
VOH
nQ OUTPUT
VOL
VM(1)
th
t su
th
t su
1/fmax
VM(1)
tW
t PHL
VM(1)
t PLH
t PLH
VM(1)
t PHL
MNA422
FAMILY
AHC
AHCT
VI INPUT
REQUIREMENTS
GND to VCC
GND to 3.0 V
VM(1)
INPUT
50% VCC
1.5 V
VM(1)
OUTPUT
50% VCC
50% VCC
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig.6 The clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up, the
nCP to nD hold times, the output transition times and the maximum clock pulse frequency.
1999 Sep 23
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet 74AHCT74.PDF ] | |
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