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PDF 74AHC164 Data sheet ( Hoja de datos )
| Número de pieza | 74AHC164 | |
| Descripción | 8-bit serial-in/parallel-out shift register | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
Rev. 03 — 24 April 2008
Product data sheet
1. General description
The 74AHC164; 74AHCT164 shift register is a high-speed Si-gate CMOS device and is
pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard No. 7A.
The 74AHC164; 74AHCT164 input signals are 8-bit serial through one of two inputs (DSA
or DSB); either input can be used as an active HIGH enable for data entry through the
other input. Both inputs must be connected together or an unused input must be tied
HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP)
and enters into output Q0, which is a logical AND of the two data inputs (DSA and DSB)
that existed one set-up time prior to the rising clock edge.
A LOW-level on the master reset (MR) input overrides all other inputs and clears the
register asynchronously, forcing all outputs LOW.
2. Features
I Balanced propagation delays
I All inputs have Schmitt-trigger actions
I Inputs accept voltages higher than VCC
I Input levels:
N For 74AHC164: CMOS level
N For 74AHCT164: TTL level
I ESD protection:
N HBM EIA/JESD22-A114E exceeds 2000 V
N MM EIA/JESD22-A115-A exceeds 200 V
N CDM EIA/JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
1 page  
NXP Semiconductors
74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
6. Functional description
Table 3. Function table[1]
Operating mode
Control
MR
Reset (clear)
L
Shift
H
CP
X
↑
Input
DSA
X
l
l
h
h
DSB
X
l
h
l
h
Output
Q0
L
L
L
L
H
Q1 to Q7
L to L
q0 to q6
q0 to q6
q0 to q6
q0 to q6
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
↑ = LOW-to-HIGH transition;
X = don’t care;
q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition.
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC
VI
IIK
IOK
IO
ICC
IGND
Tstg
Ptot
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
VI < −0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
VO = −0.5 V to (VCC + 0.5 V)
Tamb = −40 °C to +125 °C
−0.5
−0.5
[1] −20
[1] −20
−25
-
−75
−65
[2] -
+7.0
+7.0
-
+20
+25
+75
-
+150
500
V
V
mA
mA
mA
mA
mA
°C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For TSSOP14 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN14 packages: above 60 °C the value of Ptot derates linearly at 4.5 mW/K.
74AHC_AHCT164_3
Product data sheet
Rev. 03 — 24 April 2008
© NXP B.V. 2008. All rights reserved.
5 of 18
5 Page 
NXP Semiconductors
74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
VI
CP input
GND
VI
DSA, DSB input
GND
VM
t su
th
VM
t su
th
VOH
Qn output
VOL
VM
001aaf612
Fig 9.
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical voltage output levels that occur with the output load.
Data set-up and hold times
Table 8. Measurement points
Type
74AHC164
74AHCT164
Input
VM
0.5 × VCC
1.5 V
Output
VM
0.5 × VCC
0.5 × VCC
74AHC_AHCT164_3
Product data sheet
Rev. 03 — 24 April 2008
© NXP B.V. 2008. All rights reserved.
11 of 18
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet 74AHC164.PDF ] | |
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