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74ACTQ273PC fiches techniques PDF

Fairchild Semiconductor - Quiet Series Octal D-Type Flip-Flop

Numéro de référence 74ACTQ273PC
Description Quiet Series Octal D-Type Flip-Flop
Fabricant Fairchild Semiconductor 
Logo Fairchild Semiconductor 





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74ACTQ273PC fiche technique
August 1989
Revised November 1999
74ACTQ273
Quiet Series Octal D-Type Flip-Flop
General Description
The ACTQ273 has eight edge-triggered D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) and Master Reset (MR) input load and
reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D-
type input, one setup time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop’s Q
output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
The ACTQ utilizes Fairchild Quiet Seriestechnology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Seriesfeatures
GTOoutput control and undershoot corrector in addition
to a split ground bus for superior performance.
Features
s ICC reduced by 50%
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Improved latch-up immunity
s Buffered common clock and asynchronous master reset
s Outputs source/sink 24 mA
s 4 kV minimum ESD immunity
Ordering Code:
Order Number Package Number
Package Description
74ACTQ273SC
M20B
20-Lead Small Outline Integrated Circuit, JEDEC MS-013, 0.300Wide Body
74ACTQ273SJ
M20D
20-Lead Small Outline Package, EIAJ TYPE II, 5.3mm Wide
74ACTQ273MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACTQ273PC
N20A
20-Lead Plastic Dual-In-Line Package, JEDEC MS-001, 0.300Wide
Device also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
Description
D0D7
MR
Data Inputs
Master Reset
CP Clock Pulse Input
Q0Q7
Data Outputs
FACT, FACT Quiet Series, and GTOare trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010585
www.fairchildsemi.com

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