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PDF 74ACT74MTC Data sheet ( Hoja de datos )
| Número de pieza | 74ACT74MTC | |
| Descripción | Dual D-Type Positive Edge-Triggered Flip-Flop | |
| Fabricantes | Fairchild Semiconductor | |
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November 1988
Revised November 1999
74AC74 • 74ACT74
Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
The AC/ACT74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at
a voltage level of the clock pulse and is not directly related
to the transition time of the positive-going pulse. After the
Clock Pulse input threshold voltage has been passed, the
Data input is locked out and information present will not be
transferred to the outputs until the next rising edge of the
Clock Pulse input.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q
HIGH
Features
s ICC reduced by 50%
s Output source/sink 24 mA
s ACT74 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC74SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
74AC74SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC74MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC74PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT74SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
74ACT74SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT74MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT74PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D1, D2
CP1, CP2
CD1, CD2
SD1, SD2
Q1, Q1, Q2, Q2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS009920
www.fairchildsemi.com
1 page  
AC Operating Requirements for AC
Symbol
Parameter
tS Set-up Time, HIGH or LOW
Dn to CPn
tH Hold Time, HIGH or LOW
Dn to CPn
tW CPn or CDn or SDn
Pulse Width
trec Recovery Time
CDn or SDn to CP
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
VCC
(V)
(Note 8)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
AC Electrical Characteristics for ACT
TA = +25°C
CL = 50 pF
Typ
TA = −40°C to +85°C
CL = 50 pF
Guaranteed Minimum
1.5 4.0
4.5
1.0 3.0
3.0
−2.0
−1.5
0.5
0.5
0.5
0.5
3.0 5.5
7.0
2.5 4.5
5.0
−2.5
−2.0
0
0
0
0
Symbol
Parameter
fMAX
Maximum Clock
Frequency
tPLH Propagation Delay
CDn or SDn to Qn or Qn
tPHL Propagation Delay
CDn or SDn to Qn or Qn
tPLH Propagation Delay
CPn to Qn or Qn
tPHL Propagation Delay
CPn to Qn or Qn
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
VCC
(V)
(Note 9)
5.0
TA = +25°C
CL = 50 pF
Min Typ Max
145 210
TA = −40°C to +85°C
CL = 50 pF
Min Max
125
5.0 3.0 5.5 9.5 2.5 10.5
5.0 3.0 6.0 10.0 3.0 11.5
5.0 4.0 7.5 11.0 4.0 13.0.
5.0 3.5 6.0 10.0 3.0 11.5
AC Operating Requirements for ACT
Symbol
Parameter
tS Set-up Time, HIGH or LOW
Dn to CPn
tH Hold Time, HIGH or LOW
Dn to CPn
tW CPn or CDn or SDn
Pulse Width
trec Recovery Time
CDn or SDn to CP
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V
VCC
(V)
(Note 10)
5.0
5.0
5.0
5.0
TA = +25°C
CL = 50 pF
Typ
TA = −40°C to +85°C
CL = 50 pF
Guaranteed Minimum
1.0 3.0
3.5
−0.5
1.0
1.0
3.0 5.0
6.0
−2.5
0
0
Capacitance
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ Units
Conditions
4.5
35.0
pF VCC = OPEN
pF VCC = 5.0V
Units
ns
ns
ns
ns
Units
MHz
ns
ns
ns
ns
Units
ns
ns
ns
ns
5 www.fairchildsemi.com
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| PDF Descargar | [ Datasheet 74ACT74MTC.PDF ] | |
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