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PDF 74ACT74M Data sheet ( Hoja de datos )
| Número de pieza | 74ACT74M | |
| Descripción | DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR | |
| Fabricantes | STMicroelectronics | |
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74ACT74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
s HIGH SPEED:
fMAX = 250 MHz (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
s COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN), VIL = 0.8V (MAX)
s 50Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The ACT74 is an advanced high-speed CMOS
OCTAL D-TYPE FLIP FLOP WITH PRESET AND
CLEAR fabricated with sub-micron silicon gate
and double-layer metal wiring C2MOS
technology.
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of
BM
(Plastic Package)
(Micro Package)
ORDER CODES :
74ACT74B
74ACT74M
the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
It is ideal for low power applications mantaining
high speed operation similar to equivalent Bipolar
Schottky TTL.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 1997
1/11
1 page  
74ACT74
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns)
Symbol
P ar ame te r
tPLH Propagation Delay Time
tPHL CK to Q
tPLH Propagation Delay Time
tPHL PR or CLR to Q or Q
tw CK Pulse Width, HIGH
or LOW
ts Setup Time Q to CK
HIGH or LOW
th Hold Time Q to CK
HIGH or LOW
trem Removal Time PR or
CLR to CK
fMAX Maximim Clock
Frequency
(*) Voltage range is 5V ± 0.5V
Test Condition
V CC
(V)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
Value
TA = 25 oC
-40 to 85 oC
Min. Typ. Max. Min. Max.
5.0 10.0
11.0
Unit
ns
5.0 10.0
11.0 ns
1.5 5.0
6.0 ns
0.5 3.0
3.5 ns
-0.5 1.0
1.0 ns
-0.7 1.0
1.0 ns
100 250 85 MHz
CAPACITIVE CHARACTERISTICS
Symbol
P ar ame te r
Test Conditions
V CC
(V)
Value
TA = 25 oC
-40 to 85 oC
Min. Typ. Max. Min. Max.
Unit
CIN Input Capacitance
5.0
4 pF
CPD Power Dissipation
Capacitance (note 1)
5.0
43 pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to
Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/n (per circuit)
5/11
5 Page 
74ACT74
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
© 1997 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A
.
11/11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet 74ACT74M.PDF ] | |
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