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PDF 74ACT715PC Data sheet ( Hoja de datos )
| Número de pieza | 74ACT715PC | |
| Descripción | Programmable Video Sync Generator | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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November 1988
Revised December 1998
74ACT715•74ACT715-R
Programmable Video Sync Generator
General Description
The ACT715 and ACT715-R are 20-pin TTL-input compati-
ble devices capable of generating Horizontal, Vertical and
Composite Sync and Blank signals for televisions and
monitors. All pulse widths are completely definable by the
user. The devices are capable of generating signals for
both interlaced and noninterlaced modes of operation.
Equalization and serration pulses can be introduced into
the Composite Sync signal when needed.
Four additional signals can also be made available when
Composite Sync or Blank are used. These signals can be
used to generate horizontal or vertical gating pulses, cursor
position or vertical Interrupt signal.
These devices make no assumptions concerning the sys-
tem architecture. Line rate and field/frame rate are all a
function of the values programmed into the data registers,
the status register, and the input clock frequency.
The ACT715 is mask programmed to default to a Clock
Disable state. Bit 10 of the Status Register, Register 0,
defaults to a logic “0”. This facilitates (re)programming
before operation.
The ACT715-R is the same as the ACT715 in all respects
except that the ACT715-R is mask programmed to default
to a Clock Enabled state. Bit 10 of the Status Register
defaults to a logic “1”. Although completely (re)programma-
ble, the ACT715-R version is better suited for applications
using the default 14.31818 MHz RS-170 register values.
This feature allows power-up directly into operation, follow-
ing a single CLEAR pulse.
Features
s Maximum Input Clock Frequency > 130 MHz
s Interlaced and non-interlaced formats available
s Separate or composite horizontal and vertical Sync and
Blank signals available
s Complete control of pulse width via register
programming
s All inputs are TTL compatible
s 8 mA drive on all outputs
s Default RS170/NTSC values mask programmed into
registers
s ACT715-R is mask programmed to default to a Clock
Enable state for easier start-up into 14.31818 MHz
RS170 timing
Ordering Code:
Order Number Package Number
Package Description
74ACT715SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74ACT715PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT715-RSC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74ACT715-RPC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignment for DIP and SOIC
FACT™ is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010137.prf
www.fairchildsemi.com
1 page  
FIGURE 2. Vertical Waveform Specification
FIGURE 3. Equalization/Serration Interval Programming
HORIZONTAL AND VERTICAL GATING SIGNALS
Horizontal Drive and Vertical Drive outputs can be utilized
as general purpose Gating Signals. Horizontal and Vertical
Gating Signals are available for use when Composite Sync
and Blank signals are selected and the value of Bit 2 of the
Status Register is 0. The Vertical Gating signal will change
in the same manner as that specified for the Vertical Blank.
Horizontal Gating Signal Width = [REG(16) − REG(15)] ×
ckper
Vertical Gating Signal Width: = [REG(18) − REG(17)] ×
hper
CURSOR POSITION AND VERTICAL INTERRUPT
The Cursor Position and Vertical Interrupt signal are avail-
able when Composite Sync and Blank signals are selected
and Bit 2 of the Status Register is set to the value of 1. The
Cursor Position generates a single pulse of n clocks wide
during every line that the cursor is specified. The signals
are generated by logically ORing (ANDing) the active LOW
(HIGH) signals specified by the registers used for generat-
ing Horizontal and Vertical Gating signals. The Vertical
Interrupt signal generates a pulse during the vertical inter-
val specified. The Vertical Interrupt signal will change in the
same manner as that specified for the Vertical Blanking sig-
nal.
Horizontal Cursor Width = [REG(16) − REG(15)] × ckper
Vertical Cursor Width = [REG(18) − REG(17)] × hper
Vertical Interrupt Width = [REG(14) − REG(13)] × hper
5 www.fairchildsemi.com
5 Page 
Capacitance (Continued)
FIGURE 5. AC Specifications
Additional Applications Information
POWERING UP
The ACT715 default value for Bit 10 of the Status Register
is 0. This means that when the CLEAR pulse is applied and
the registers are initialized by loading the default values the
CLOCK is disabled. Before operation can begin, Bit 10
must be changed to a 1 to enable CLOCK. If the default
values are needed (no other programming is required) then
Figure 6 illustrates a hardwired solution to facilitate the
enabling of the CLOCK after power-up. Should control sig-
nals be difficult to obtain, Figure 7 illustrates a possible
solution to automatically enable the CLOCK upon power-
up. Use of the ACT715-R eliminates the need for most of
this circuitry. Modifications of the Figure 7 circuit can be
made to obtain the lone CLEAR pulse still needed upon
power-up.
Note that, although during a Vectored Restart none of the
preprogrammed registers are affected, some signals are
affected for the duration of one frame only. These signals
are the Horizontal and Vertical Drive signals. After a Vec-
tored Restart the beginning of these signals will occur at
the first CLK. The end of the signals will occur as pro-
grammed. At the completion of the first frame, the signals
will resume to their programmed start and end time.
PREPROGRAMMING “ON-THE-FLY”
Although the ACT715 and ACT715-R are completely pro-
grammable, certain limitations must be set as to when and
how the parts can be reprogrammed. Care must be taken
when reprogramming any End Time registers to a new
value that is lower than the current value. Should the repro-
gramming occur when the counters are at a count after the
new value but before the old value, then the counters will
continue to count up to 4096 before rolling over.
For this reason one of the following two precautions are
recommended when reprogramming “on-the-fly”. The first
recommendation is to reprogram horizontal values during
the horizontal blank interval only and/or vertical values dur-
ing the vertical blank interval only. Since this would require
delicate timing requirements the second recommendation
may be more appropriate.
The second recommendation is to program a Vectored
Restart as the final step of reprogramming. This will ensure
that all registers are set to the newly programmed values
and that all counters restart at the first CLK position. This
will avoid overrunning the counter end times and will main-
tain the video integrity.
11 www.fairchildsemi.com
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet 74ACT715PC.PDF ] | |
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