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PDF 74ACT323 Data sheet ( Hoja de datos )
| Número de pieza | 74ACT323 | |
| Descripción | 8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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June 1988
Revised October 1998
74ACT323
8-Bit Universal Shift/Storage Register with
Synchronous Reset and Common I/O Pins
General Description
The ACT323 is an 8-bit universal shift/storage register with
3-STATE outputs. Parallel load inputs and flip-flop outputs
are multiplexed to minimize pin count. Separate serial
inputs and outputs are provided for Q0 and Q7 to allow
easy cascading. Four operation modes are possible: hold
(store), shift left, shift right and parallel load.
Features
s ICC and IOZ reduced by 50%
s Common parallel I/O for reduced pin count
s Additional serial inputs and outputs for expansion
s Four operating modes: shift left, shift right, load and
store
s 3-STATE outputs for bus-oriented applications
s Outputs source/sink 24 mA
s TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74ACT323PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment
for DIP
FACT™ is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS009787.prf
Pin Descriptions
Pin Name
Description
CP Clock Pulse Input
DS0
DS7
S0, S1
SR
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Synchronous Reset Input
OE1, OE2
I/O0–I/O7
3-STATE Output Enable Inputs
Multiplexed Parallel Data Inputs or
3-STATE Parallel Data Outputs
Q0, Q7
Serial Outputs
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1 page  
AC Electrical Characteristics
Symbol
Parameter
fmax Maximum Input Frequency
tPLH Propagation Delay
CP to Q0 or Q7
tPHL Propagation Delay
CP to Q0 or Q7
tPLH Propagation Delay
CP to I/On
tPHL Propagation Delay
CP to I/On
tPZH Output Enable Time
tPZL Output Enable Time
tPHZ Output Disable Time
tPLZ Output Disable Time
Note 4: Voltage Range 5.0 is 5.0V ±0.5V
VCC
(V)
(Note 4)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
AC Operating Requirements
TA = 25°C
CL = 50 pF
Min Typ Max
120 125
5.0 9.0 12.5
5.0 9.0 13.5
5.0 8.5 12.5
6.0
10.0
14.5
3.5 7.5 11.0
3.5 7.5 11.5
4.0 8.5 12.5
3.0 8.0 11.5
TA = −40°C to +85°C
CL = 50 pF
Min Max
110
4.0 14.0
4.5 15.0
4.5 14.5
5.0 16.0
3.0 12.5
3.0 13.0
3.0 13.5
2.5 12.5
Symbol
Parameter
tS Setup Time, HIGH or LOW
S0 or S1 to CP
tH Hold Time, HIGH or LOW
S0 or S1 to CP
tS Setup Time, HIGH or LOW
I/On, DS0, DS7 to CP
tH Hold Time, HIGH or LOW
I/On, DS0, DS 7 to CP
tS Setup Time, HIGH or LOW
SR to CP
tH Hold Time, HIGH or LOW
SR to CP
tW CP Pulse Width
HIGH or LOW
Note 5: Voltage Range 5.0 is 5.0V ±0.5V
Capacitance
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance
VCC
(V)
(Note 5)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
TA = 25°C
TA = −40°C to +85°C
CL = 50 pF
CL = 50 pF
VCC = +5.0V
VCC = +5.0V
Typ Guaranteed Minimum
2.0 5.0
5.0
0 1.5
1.5
1.0 4.0
4.5
0 1.0
1.0
1.0 2.5
2.5
0 1.0
1.0
2.0 4.0
4.5
Typ Units
Conditions
4.5 pF VCC = OPEN
170 pF VCC = 5.0V
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
5 www.fairchildsemi.com
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| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet 74ACT323.PDF ] | |
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