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PDF 74ACT273 Data sheet ( Hoja de datos )
| Número de pieza | 74ACT273 | |
| Descripción | Octal D-Type Flip-Flop | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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November 1988
Revised August 2000
74AC273 • 74ACT273
Octal D-Type Flip-Flop
General Description
The AC273 and ACT273 have eight edge-triggered D-type
flip-flops with individual D-type inputs and Q outputs. The
common buffered Clock (CP) and Master Reset (MR) input
load and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D-
type input, one setup time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop’s Q
output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
Features
s Ideal buffer for microprocessor or memory
s Eight edge-triggered D-type flip-flops
s Buffered common clock
s Buffered, asynchronous master reset
s See 377 for clock enable version
s See 373 for transparent latch version
s See 374 for 3-STATE version
s Outputs source/sink 24 mA
s 74ACT273 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC273SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74AC273SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC273MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC273PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACT273SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACT273SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT273MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT273PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation DS009954
www.fairchildsemi.com
1 page  
DC Electrical Characteristics for ACT
Symbol
Parameter
VIH Minimum HIGH Level
Input Voltage
VIL Maximum LOW Level
Input Voltage
VOH Minimum HIGH Level
Output Voltage
VCC
TA = +25°C
TA = −40°C to +85°C
(V) Typ
Guaranteed Limits
4.5 1.5
2.0
2.0
5.5 1.5
2.0
2.0
4.5 1.5
0.8
0.8
5.5 1.5
0.8
0.8
4.5 4.49
4.4
4.4
5.5 5.49
5.4
5.4
VOL Maximum LOW Level
Output Voltage
4.5 3.86
5.5 4.86
4.5 0.001
0.1
5.5 0.001
0.1
3.76
4.76
0.1
0.1
4.5 0.36
5.5 0.36
IIN Maximum Input
Leakage Current
5.5
±0.1
ICCT
IOLD
IOHD
ICC
Maximum
ICC/Input
Minimum Dynamic
Output Current (Note 8)
Maximum Quiescent
Supply Current
5.5 0.6
5.5
5.5
5.5
4.0
Note 7: All outputs loaded; thresholds on input associated with output under test.
Note 8: Maximum test duration 2.0 ms, one output loaded at a time.
0.44
0.44
±1.0
1.5
75
−75
40.0
Units
Conditions
V VOUT = 0.1V
or VCC − 0.1V
V VOUT = 0.1V
or VCC − 0.1V
V IOUT = −50 µA
VIN = VIL or VIH
V IOH = −24 mA
IOH = −24 mA (Note 7)
V IOUT = 50 µA
VIN = VIL or VIH
V IOL = 24 mA
IOL = 24 mA (Note 7)
µA VI = VCC, GND
mA VI = VCC − 2.1V
mA VOLD = 1.65V Max
mA VOHD = 3.85V Min
µA VIN = VCC
or GND
AC Electrical Characteristics for ACT
Symbol
Parameter
fMAX
Maximum Clock Frequency
tPLH Propagation Delay
tPHL
CP to Qn
tPHL Propagation Delay
MR to Qn
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
VCC
(V)
(Note 9)
2.0
5.0
5.0
TA = +25°C
CL = 50 pF
Min Typ Max
125 189
1.5 6.5 8.5
1.5 7.0 9.0
TA = −40°C to +85°C
CL = 50 pF
Min Max
110
1.5 9.0
1.5 8.5
Units
MHz
ns
ns
5 www.fairchildsemi.com
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74ACT273.PDF ] | |
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