PDF EM78P447S Data sheet ( Hoja de datos )

Número de pieza	EM78P447S
Descripción	8-bit microprocessor with low-power and high-speed CMOS technology
Fabricantes	ELAN Microelectronics Corp
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No Preview Available ! EM78P447S I. GENERAL DESCRIPTION EM78P447S is an 8-bit microprocessor with low-power and high-speed CMOS technology. There is a 409613- bit Electrical One Time Programmable Read Only Memory (OTP-ROM) within it. It provides a PROTECTION bit to prevent a user’s code from intruding as well as 8 other OPTION bits to match the user’s requirements. Because of the OTP-ROM, the EM78P447S offers users a convenient way to develop and verify their programs. Moreover, a user’s developed code can be programmed easily by an EMC writer. II. FEATURES • Operating voltage range: 2.2V~5.5V • Available in temperature range: 0°C~70°C • Operating frequency range: DC ~ 20MHz • Low power consumption: less than 2.2 mA at 5V/4MHz * typical of 30µA at 3V/32KHz * typical of 1µA during the sleep mode • 4096 x 13 bits on chip ROM • 148 x 8 bits on chip registers (SRAM) • 3 bi-directional I/O ports • 5 level stacks for subroutine and interrupt • 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt • Power-down mode (SLEEP mode) • Two available interruptions * TCC overflow interrupt * External interrupt(INT pin) • Programmable free running watchdog timer • 10 programmable pull-high I/O pins • 2 programmable R-option I/O pins • 2 programmable open-drain I/O pins • Two clocks per instruction cycle • 99.9% single instruction cycle commands • Package type: * 28 pin DIP and SOIC (EM78P447SA) * 32 pin DIP and SOIC (EM78P447SB) * This specification is subject to be changed without notice. 12.29.1999 B3-1 1 page EM78P447S CALL PC A11 A10 A9 A8 A7 ~ A0 RET RETI RETL Stack 1 Stack 2 Stack 3 Stack 4 Stack 5 000 00 Page 0 3FF 400 01 Page 1 7FF 800 10 Page 2 001: Hareware interrupt location 002: Software interrupt (INT instruction) location FFF: Reset location BFF C00 11 Page 3 FFF 4. R3 (Status Register) Fig. 3 Program counter organization 76 5 43210 GP PS1 PS0 T P Z DC C • Bit 0 (C) Carry flag • Bit 1 (DC) Auxiliary carry flag • Bit 2 (Z) Zero flag. Set to “1” if the result of an arithmetic or logic operation is zero. • Bit 3 (P) Power-down bit. Set to 1 during power-on or by a “WDTC” command and reset to 0 by a “SLEP” command. • Bit 4 (T) Time-out bit. Set to 1 by the “SLEP” and “WDTC” commands, or during power-up and reset to 0 by WDT time-out. • Bit 5 (PS0) ~ 6 (PS1) Page-selecting bits. PS0~PS1 are used to select a program memory page. When executing “JMP”, “CALL”, or other instructions which cause the program counter to be changed (e.g. MOV R2,A), PS0~PS1 are loaded to the 11th and 12th bits of the program counter which would select one of the available program memory pages. Note that RET, RETL and RETI instructions do not change the PS0~PS1 bits. That is, the return will be always to the page from the place where the subroutine was called, regardless of the current setting of PS0~PS1 bits. * This specification is subject to be changed without notice. 12.29.1999 B3-5 5 Page EM78P447S VI.4 I/O Ports The I/O registers, Port 5, Port 6 and Port 7, are bi-directional tri-state I/O ports. The function of Pull-high, R-option and Open-drain can be enabled internally by CONT and IOCE respectively. There is an input status changed interrupt (or wake-up) function on Port 6, P74 and P75. Each I/O pin can be defined as “input” or “output” pin by the I/O control register (IOC5 ~ IOC7). The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits for Port 5, Port 6 and Port 7 are shown in Fig. 7 (a) & (b) respectively. CLK(=Fosc/2 or Fosc/4) Data Bus TCC Pin TE WDT WTE (in IOCE) 0 M U 1X 1M U 0X SYNC 2 cycles TCC(R1) TS PAB TCC overflow interrupt 0M U 1X PAB 8-bit Counter 8-to-1 MUX 01 MUX PSR0~PSR2 PAB WDT time-out Fig. 6 Block diagram of TCC and WDT PCRD Q PR D CLK Q CL PCWR PORT 0M 1U X Q PR D CLK Q CL PDWR PDRD IOD Fig. 7(a) The circuit of I/O port and I/O control register * This specification is subject to be changed without notice. 12.29.1999 B3-11 11 Page

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