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PDF EM73361A Data sheet ( Hoja de datos )
| Número de pieza | EM73361A | |
| Descripción | 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT | |
| Fabricantes | ELAN Microelectronics Corp | |
| Logotipo |  |
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EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
GENERAL DESCRIPTION
EM73361A is an advanced single chip CMOS 4-bit micro-controller. It contains 3K-byte ROM, 52-nibble RAM,
4-bit ALU, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/counters for the kernel function.
EM73361A also contains 3 interrupt sources, 1 input port, 4 bidirection I/O ports, built-in watch-dog-timer
counter, tone generator and LCD driver (27x3 to 13x3).
Except low-power consumption and high speed, EM73361A also have a sleep mode operation for power saving.
FEATURES
• Operation voltage
: 2.2V to 3.6V(clock frequency : 32K Hz).
• Clock source
: Single clock system for crystal, connect a external resistor or external clock
source available by mask option.
• Instruction set
: 109 powerful instructions.
• Instruction cycle time : 122µs for 32K Hz.
• ROM capacity
: 3072 X 8 bits.
• RAM capacity
: 52 X 4 bits.
• Input port
: 1 port (P0)(Pull-up and pull-down resistor with wakeup function available by
mask option).
• Bidirection port
: 4 ports (P4, P5, P6, P7) are available by mask option. (each I/O pin is push-pull
and open-drain available by mask option) P4.0 is high current pin (P4.0 and
TONE available by mask option). P4.2~P4.3, P5, P6 and P7 are shared with
SEG26-SEG13 by mask option.
• 12-bit timer/counter
: Two 12-bit timer/counters are programmable for timer mode.
• Low voltage reset (LVR) : Reset at 1.5V, and reset release at 1.8V.
• Tone generator
: There is a built-in tone generator.
• Built-in time base counter : 22 stages.
• Subroutine nesting
: Up to 13 levels.
• Interrupt
: External . . . . . 2 External interrupt (INT0, INT1).
Internal . . . . . . 2 Timer overflow interrupts.
1 Time base interrupt.
• LCD driver
: 27 X 3 to 13 X 3 dots available by mask option. Capacitor divider and resistor
divider are available by mask option.1/3, 1/2 and static three kinds of duty (1/2
bias) selectable. The programming method of LCD driver is I/O mapping.
• Built-in watch-dog-timer : The WDT is enabled or disabled by mask option.
• Power saving function : Sleep mode and Hold mode.
• Package type
: EM73361AAH
Chip form 46 pins.
EM73361AAQ
QFP 100 pins.
APPLICATIONS
EM73361A is suitable for application in family appliance, consumer products, hand held games and the toy
controller.
* This specification are subject to be changed without notice.
10.8.2001 1
1 page  
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
User's program and fixed data are stored in the program ROM. User's program is according the PC value
to send next executed instruction code. Fixed data can be read out by table-look-up instruction.
Table-look-up instruction is depended on the Data Pointer ( DP ) to indicate to ROM address, then to get the
ROM code data.
LDAX
LDAXI
Acc ← ROM[DP]L
Acc ← ROM[DP]H,DP+1
DP is a 12-bit data register which can store the program ROM address to be the pointer for the ROM code data.
First, user load ROM address into DP by instruction "STADPL, STADPM, STADPH", then user can get the
lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction "LDAXI".
PROGRAM EXAMPLE: Read out the ROM code of address 777h by table-look-up instruction.
LDIA #07h;
STADPL
STADPM
STADPH
:
; [DP]L ← 07h
;
[DP]
M
←
07h
; [DP]H ← 07h, Load DP=777h
LDL #00h;
LDH #03h;
LDAX
; ACC ← 6h
STAMI ; RAM[30] ← 6h
LDAXI ; ACC ← 5h
STAM
; RAM[31] ← 5h
;
ORG 777h
DATA 56h;
:
DATA RAM ( 52-nibble )
There is total 52 - nibble data RAM from address 00 to 33h
Data RAM includes 3 parts: zero page region, stacks and data area.
Increment
Address
00h - 0Fh Level 0 Level 1 Level 2 Level 3
10h - 1Fh Level 4 Level 5 Level 6 Level 7
20h - 2Fh Level 8 Level 9 Level 10 Level 11
30h - 33h Level 12
ZERO- PAGE:
Stack
Zero-page
From 00h to 0Fh is the location of zero-page. It is used as the pointer in zero -page addressing mode for the
instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y".
PROGRAM EXAMPLE: To wirte immediate data "07h" to address "03h" of RAM and to clear bit 2 of RAM.
STD #07h, 03h ; RAM[03] ← 07h
CLR 0Eh,2 ; RAM[0Eh]2 ← 0
STACK:
There are 13 - level (maximum) stack for user using for subroutine (including interrupt and CALL). User
can assign any level be the starting stack by giving the level number to stack pointer (SP).
* This specification are subject to be changed without notice.
10.8.2001 5
5 Page 
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
PROGRAM EXAMPLE: Store immediate data #Ah into RAM of address 35h.
LDL #5h;
LDH #3h;
STDMI #0Ah; RAM[35] ← Ah
(3) For instruction : SELP, CLPL, TFPL, L regieter be a pointer to indicate the bit of I/O port.
When LR = 0 - 1, indicate P4.0 - P4.1.
PROGRAM EXAMPLE: To set bit 1 of Port4 to "1"
LDL #01h;
SEPL ; P4.1 ← 1
STACK POINTER (SP)
Stack pointer is a 4-bit register which stores the present stack level number.
Before using stack, user must set the SP value first, CPU will not initiate the SP value after reset condition
. When a new subroutine is accepted, the SP will be decreased one automatically, in another word, if
returning from a subroutine, the SP will be increased one .
The data transfer between ACC and SP is by instruction of "LDASP" and "STASP".
DATA POINTER (DP)
Data pointer is a 12-bit register which stores the address of ROM can indicate the ROM code data
specified by user (refer to data ROM).
CLOCK AND TIMING GENERATOR
The clock generator is supported by a single clock system, the clock source comes from crystal (resonator)
or RC oscillation, the working frequency range is 32 KHz to 100 KHz depending on the working voltage.
CLOCK AND TIMING GENERATOR STRUCTURE
The clock generator connects outside compoments ( crystal or resonator by XIN and XOUT pin for crystal
osc type, capacitor for RC osc type, these two type is decided by mask option) the clock generator generates
a basic system clock "fc".
When CPU sleeping, the clock generator will be stoped until the sleep condition released.
The system clock control generates 4 basic phase signals ( S1, S2, S3, S4 ) and system clock .
Mask option
sleep
Mask option for choose Crystal or RC oscillation
XIN/XCILNK
XOUT
fc
clock generator
System clock control
System clock
S1 S2 S3 S4
* This specification are subject to be changed without notice.
10.8.2001 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EM73361A.PDF ] | |
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