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PDF EM73201 Data sheet ( Hoja de datos )
| Número de pieza | EM73201 | |
| Descripción | 4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT | |
| Fabricantes | ELAN Microelectronics Corp | |
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EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
Preliminary
GENERAL DESCRIPTION
EM73201 is an advanced single chip CMOS 4-bit micro-controller. It contains 2K-byte ROM, 52-nibble RAM,
4-bit ALU, 13-level subroutine nesting, 22-stage time base, one 12-bit timer/counter for the kernel function.
EM73201 also contains 5 interrupt sources, 4 I/O ports (including 1 input port, 1 output port for LED driving,
2 bidirection I/O ports) built-in watch-dog-time counter and one high frequency clock output for modulating
infrared signal.
Except low-power consumption and high speed, EM73201 also have a sleep and hold mode operation for the
power saving function.
EM73201 is suitable for application in family appliance, consumer products and toy controller.
FEATURES
Operation voltage
: 2.4V to 6.0V (clock frequency: 32 KHz to 5 MHz)
Clock source
: Single clock system for RC , Crystal and external clock source, available by
mask option.
Instruction set
: 109 powerful instructions.
Instruction cycle time : Up to 2µs for 4.19MHz .
ROM capacity
: 2048 x 8 bits.
RAM capacity
: 52 x 4 bits.
Input port
: 1 port (P0).
Output port
: 1 port (P1).
Bidirection I/O port
: 2 ports (P7,P8).
12-bit timer/counter
: One 12-bit timer/counter is programmable for timer, even counter and pulse
width measurement mode.
Built-in time base counter : 22 stages.
Subroutine nesting
: Up to 13 levels.
Interrupt
: External interrupt . . . . . . 2 input interrupt sources.
Internal interrupt . . . . . . 1 timer overflow interrupt,
1 time base interrupt.
The built-in watch-dog-timer counter is available by mask option.
Low voltage reset is available by mask option.
High frequency clockout: Programmable high frequency clock output for modulating infrared signal.
Power saving function : Sleep mode and Hold mode.
Package type
: EM73201H
Chip form 22 pins.
EM73201AP DIP
18 pins.
EM73201BK SKINNY 22 pins.
EM73201CP DIP
16 pins.
APPLICATIONS
EM73201 is suitable for application in family appliance, consumer products and the toy controller.
* This specification are subject to be changed without notice.
7.20.1999 1
1 page  
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
STAMI
LDAXI
; RAM[30] ← 6h
; ACC ← 5h
Preliminary
STAM
:
; RAM[31] ← 5h
ORG 777h
DATA 56h;
:
DATA RAM ( 52-nibble )
There is total 52 - nibble data RAM from address 00 to 33h
Data RAM includes 3 parts: zero page region, stacks and data area.
Increment
Address
00h - 0Fh Level 0 Level 1 Level 2 Level 3
10h - 1Fh Level 4 Level 5 Level 6 Level 7
20h - 2Fh Level 8 Level 9 Level 10 Level 11
30h - 33h Level 12
Stack
Zero-page
ZERO- PAGE:
From 00h to 0Fh is the location of zero-page. It is used as the pointer in zero-page addressing mode for the
instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y".
PROGRAM EXAMPLE:
To wirte immediate data "07h" to address "03h" of RAM and to clear bit 2 of RAM.
STD #07h, 03h ; RAM[03] ← 07h
CLR 0Eh,2 ; RAM[0Eh]2 ← 0
STACK:
There are 13 - level (maximum) stack for user using for subroutine (including interrupt and CALL). User
can assign any level be the starting stack by giving the level number to stack pointer (SP).
When user using any instruction of CALL or subroutine, before entry the subroutine, the previous PC address
will be saved into stack until return from those subroutines, the PC value will be restored by the data saved
in stack.
DATA AREA:
Except the special area used by user, the whole RAM can be used as data area for storing and loading general
data.
ADDRESSING MODE
(1) Indirect addressing mode:
Indirect addressing mode indicates the RAM address by specified HL register.
For example: LDAM ; Acc ← RAM[HL]
STAM ; RAM[HL] ← Acc
(2) Direct addressing mode:
Direct addressing mode indicates the RAM address by immediate data.
* This specification are subject to be changed without notice.
7.20.1999 5
5 Page 
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
Preliminary
LDL #5h;
LDH #3h;
STDMI #0Ah; RAM[35] ← Ah
(3) For instruction : SELP, CLPL, TFPL, L regieter be a pointer to indicate the bit of I/O port.
When LR = C - F, indicate P7.0 - P7.3
PROGRAM EXAMPLE: To set bit 2 of Port7 to "1"
LDL #0Eh;
SEPL ; P7.2 ← 1
STACK POINTER (SP)
Stack pointer is a 4-bit register which stores the present stack level number.
Before using stack, user must set the SP value first, CPU will not initiate the SP value after reset condition
. When a new subroutine is accepted, the SP will be decreased one automatically, in another word, if
returning from a subroutine, the SP will be increased one .
The data transfer between ACC and SP is by instruction of "LDASP" and "STASP".
DATA POINTER (DP)
Data pointer is a 12-bit register which stores the address of ROM can indicate the ROM code data
specified by user (refer to data ROM).
CLOCK AND TIMING GENERATOR
The clock generator is supported by a single clock system, the clock source comes from crystal (resonator
or RC oscillation is decided by mask option . the working frequency range is 32 K Hz to 5 MHz depending
on the working voltage.
CLOCK AND TIMING GENERATOR STRUCTURE
The clock generator connects outside compoments ( crystal or resonator by XIN and XOUT pin for crystal
osc type, Resistor and capacitor by CLK pin for RC osc type, these two type is decided by mask option ).
the clock generator generates a basic system clock "fc".
When CPU sleeping, the clock generator will be stoped until the sleep condition released.
The system clock control generates 4 basic phase signals ( S1, S2, S3, S4 ) and system clock .
XIN/CLK
XOUT
Mask option
sleep
Mask option for choose Crystal or RC oscillation
fc
clock generator
System clock control
System clock
S1 S2 S3 S4
* This specification are subject to be changed without notice.
7.20.1999 11
11 Page | ||
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