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Número de pieza | HYB18RL25632AC | |
Descripción | 256 Mbit DDR Reduced Latency DRAM | |
Fabricantes | Infineon Technologies AG | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de HYB18RL25632AC (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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HYB18RL25616AC
Graphics & Speciality DRAMs
256 Mbit DDR Reduced Latency DRAM
Version 1.60
July 2003
1 page HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
1 Overview
1.1 Features
z 256 Megabit (256M)
z 0.17µm process technology
z Cyclic bank addressing for maximum data out bandwidth
z Organization 8M x 32, 16M x 16 in 8 banks
z Non-multiplexed addresses
z Non-interruptible sequential bursts of 2 (2-bit prefetch) and 4 (4-bit prefetch), DDR
z Up to 600Mb/sec/pin data rate
z Programmable Read Latency (RL) of 5..6
z Data valid signal (DVLD) activated as Read Data is available
z Data Mask signals (DM0 / DM1) to mask first and second part of write data burst
z IEEE 1149.1 compliant JTAG Boundary Scan
z Pseudo-HSTL 1.8V IO Supply
z Internal autoprecharge
z Refresh requirements: 32ms at 100°C junction temperature (8k refresh for each bank, 64k refresh
commands must be issued in total each 32ms)
z Package T-FBGA 144
z 2.5V VEXT, 1.8V VDD, 1.8V VDDQ
Table 1 Key timing parameters (Configuration Example x32, x16 device)
Speed Sort
-3.3
-4.0
-5.0 Units
Frequency
300
250
200 MHz
26.7 28.0 25.0 ns
tRC 8 7 5 cycles
Read latency
6
5
5 cyles
Version 1.60
Page 5
Infineon Technologies
This specification is preliminary and subject to change without notice
5 Page HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
1.4 Functional Block Diagram
Figure 4 Functional Block Diagram 8M x 32 Configuration
Column Address
Counter
A0-A18, B0, B1, B2
Column Address Buffer
Row Address Buffer
Row Decoder
Memory Array
Bank 0
Row Decoder
Memory Array
Bank 1
Row Decoder
Memory Array
Bank 2
Refresh Counter
Row Decoder
Memory Array
Bank 3
Row Decoder
Memory Array
Bank 4
Row Decoder
Memory Array
Bank 5
Row Decoder
Memory Array
Bank 6
Row Decoder
Memory Array
Bank 7
Output Data Valid
Data read strobe
DVLD
DQS[3:0], DQS#[3:0]
Input Buffers
Output Buffers
DQ0-DQ31
Note: When the BL4 setting is used, A18 is a "Don’t Care"
Control Logic and Timing Generators
Version 1.60
Page 11
Infineon Technologies
This specification is preliminary and subject to change without notice
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet HYB18RL25632AC.PDF ] |
Número de pieza | Descripción | Fabricantes |
HYB18RL25632AC | 256 Mbit DDR Reduced Latency DRAM | Infineon Technologies AG |
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