PDF HY57V658020BTC-75 Data sheet ( Hoja de datos )

Número de pieza	HY57V658020BTC-75
Descripción	4 Banks x 2M x 8Bit Synchronous DRAM
Fabricantes	Hynix Semiconductor
Logotipo
Hay una vista previa y un enlace de descarga de HY57V658020BTC-75 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas
No Preview Available ! HY57V658020B 4 Banks x 2M x 8Bit Synchronous DRAM DESCRIPTION The Hynix HY57V658020B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V658020B is organized as 4banks of 2,097,152x8. HY57V658020B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro- nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.) FEATURES • Single 3.3±0.3V power supply • All device pins are compatible with LVTTL interface • JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch • All inputs and outputs referenced to positive edge of sys- tem clock • Data mask function by DQM • Internal four banks operation • Auto refresh and self refresh • 4096 refresh cycles / 64ms • Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst • Programmable CAS Latency ; 2, 3 Clocks ORDERING INFORMATION Part No. HY57V658020BTC-75 HY57V658020BTC-8 HY57V658020BTC-10P HY57V658020BTC-10S HY57V658020BTC-10 HY57V658020BLTC-75 HY57V658020BLTC-8 HY57V658020BLTC-10P HY57V658020BLTC-10S HY57V658020BLTC-10 Clock Frequency 133MHz 125MHz 100MHz 100MHz 100MHz 133MHz 125MHz 100MHz 100MHz 100MHz Power Organization Normal 4Banks x 4Mbits x4 Low power Interface LVTTL Package 400mil 54pin TSOP II This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.6/Nov. 01 1 1 page CAPACITANCE (TA=25°C, f=1MHz) Parameter Input capacitance Data input / output capacitance Pin CLK A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM DQ0 ~ DQ7 OUTPUT LOAD CIRCUIT Symbol CI1 CI2 CI/O Min 2 2.5 2 HY57V658020B Max 4 5 6.5 Unit pF pF pF Output Vtt=1.4V RT=250 Ω Output 50pF 50pF DC Output Load Circuit AC Output Load Circuit DC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3V) Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Symbol ILI ILO VOH VOL Min. -1 -1 2.4 - Note : 1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V 2.DOUT is disabled, VOUT=0 to 3.6V Max 1 1 - 0.4 Unit uA uA V V Note 1 2 IOH = -4mA IOL = +4mA Rev. 1.6/Nov. 01 5 5 Page COMMAND TRUTH TABLE HY57V658020B Command CKEn-1 CKEn CS Mode Register Set No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Burst Stop DQM Auto Refresh Burst-READ-Single-WRITE Self Refresh1 Entry Exit H H H H H H H H H H H L Precharge power down Entry H Exit L Clock Suspend Entry Exit H L XL H X L XL XL XL XL XL HL XL LL H H L H L L H H L H L L H RAS CAS WE DQM ADDR A10/ AP BA LLLX OP code XXX X HHH X L HHX RA V L H L H X CA H V L H L L X CA H V HX LHLX X LV HHL X X X VX L LHX X L L L X A9 Pin High (Other Pins OP code) L LHX XXX X HHH X XXX X HHH XXX X HHH X XXX X VVV X XX Note Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation Rev. 1.6/Nov. 01 11 11 Page

Páginas	Total 12 Páginas
PDF Descargar	[ Datasheet HY57V658020BTC-75.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
HY57V658020BTC-75	4 Banks x 2M x 8Bit Synchronous DRAM	Hynix Semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar