PDF HY57V653220BTC-5 Data sheet ( Hoja de datos )

Número de pieza	HY57V653220BTC-5
Descripción	4 Banks x 512K x 32Bit Synchronous DRAM
Fabricantes	Hynix Semiconductor
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No Preview Available ! HY57V653220B 4 Banks x 512K x 32Bit Synchronous DRAM DESCRIPTION The Hynix HY57V653220B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY57V653220B is organized as 4banks of 524,288x32. HY57V653220B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out- puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.) FEATURES • JEDEC standard 3.3V power supply • Auto refresh and self refresh • All device pins are compatible with LVTTL interface • 4096 refresh cycles / 64ms • JEDEC standard 400mil 86pin TSOP-II with 0.5mm of • Programmable Burst Length and Burst Type pin pitch - 1, 2, 4, 8 or full page for Sequential Burst • All inputs and outputs referenced to positive edge of system clock - 1, 2, 4 or 8 for Interleave Burst • Data mask function by DQM0,1,2 and 3 • Programmable CAS Latency ; 2, 3 Clocks • Internal four banks operation • Burst Read Single Write operation ORDERING INFORMATION Part No. Clock Frequency HY57V653220BTC-5 HY57V653220BTC-55 HY57V653220BTC-6 HY57V653220BTC-7 HY57V653220BTC-8 HY57V653220BTC-10P HY57V653220BTC-10 200MHz 183MHz 166MHz 143MHz 125MHz 100MHz 100MHz Power Normal Organization Interface Package 4Banks x 512Kbits x32 LVTTL 400mil 86pin TSOP II This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.1.6/Dec. 01 1 1 page CAPACITANCE (TA=25°C, f=1MHz, VDD=3.3V) Parameter Input capacitance Data input / output capacitance Pin CLK A0 ~ A10, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM0~3 DQ0 ~ DQ31 OUTPUT LOAD CIRCUIT Symbol CI1 CI2 CI/O Min 2.5 2.5 4 HY57V653220B Max Unit 4 pF 5 pF 6.5 pF Output Vtt=1.4V RT=500 Ω 30pF Output Z0 = 50Ω Vtt=1.4V RT=50 Ω 30pF DC Output Load Circuit AC Output Load Circuit DC CHARACTERISTICS I (DC operating conditions unless otherwise noted) Parameter Input leakage current Output leakage current Output high voltage Output low voltage Symbol ILI ILO VOH VOL Min. -1 -1.5 2.4 - Note : 1.VIN = 0 to 3.6V, All other pins are not under test = 0V 2.DOUT is disabled, VOUT=0 to 3.6V Max 1 1.5 - 0.4 Unit uA uA V V Note 1 2 IOH = -2mA IOL = +2mA Rev.1.6/Dec. 01 5 5 Page HY57V653220B COMMAND TRUTH TABLE Command Mode Register Set No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Burst Stop DQM Auto Refresh Burst-READ-Single-WRITE Self Refresh1 Entry Exit Precharge power down Entry Exit Clock Suspend Entry Exit CKEn-1 CKEn CS H XL H HX L H XL H XL H XL H XL H XL H H HL H XL H LL H LH L H HL L H LH L H HL L LH RAS CAS WE DQM ADDR A10/ AP BA LLLX XXX X HHH OP code X L HHX RA V L H L H X CA H V L H L L X CA H V HX LHLX X LV HHL X X X VX L LHX X L L L X A9 Pin High (Other Pins OP code) L LHX XXX X HHH XXX X HHH XXX X HHH X X XXX X VVV XX X Note Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation Rev.1.6/Dec. 01 11 11 Page

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