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PDF HY57V161610DTC-6I Data sheet ( Hoja de datos )
| Número de pieza | HY57V161610DTC-6I | |
| Descripción | 2 Banks x 512K x 16 Bit Synchronous DRAM | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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HY57V161610D
2 B a n k s x 5 1 2 K x 1 6 B it S y n c h r o n o u s D R A M
DESCRIPTION
THE Hynix HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the Mobile applications
which require low power consumption and industrial temperature range. HY57V161610D is organized as 2banks of
524,288x16.
HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band-
width. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or
write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipeline
design is not restricted by a `2N` rule.)
FEATURES
• S i n g l e 3 . 0 V t o 3 . 6 V p o w e r s u p p l y Note1)
• All device pins are compatible with LVTTL interface
• JEDEC standard 400mil 50pin TSOP-II with 0.8mm
of pin pitch
• All inputs and outputs referenced to positive edge of
system clock
• Data mask function by UDQM/LDQM
• Internal two banks operation
• Auto refresh and self refresh
• 4096 refresh cycles / 64ms
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 and Full Page for Sequence Burst
- 1, 2, 4 and 8 for Interleave Burst
• Programmable CAS Latency ; 1, 2, 3 Clocks
ORDERING INFORMATION
Part No.
HY57V161610DTC-55I
HY57V161610DTC-6I
HY57V161610DTC-7I
HY57V161610DTC-10I
Clock Frequency
183MHz
166MHz
143MHz
100MHz
Organization
Interface
2Banks x 512Kbits x 16
LVTTL
Package
400mil
50pin TSOP II
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied
Rev. 0.2/Aug.01
1 page  
C A P A C I T A N C E (TA=25°C, f=1MHz)
Parameter
Input capacitance
Data input / output capacitance
Pin
CLK
A0 ~ A10, BA
CKE, C S, RAS, C A S, W E, UDQM, LDQM
DQ0 ~ DQ15
Symbol
CI1
CI2
C I/O
OUTPUT LOAD CIRCUIT
HY57V161610D
Min
Max
Unit
2.5 4 pF
2.5 5 pF
4 6.5 pF
Output
V t t= 1 . 4 V
R T=250 Ω
3 0pF
Output
3 0pF
DC Output Load Circuit
AC Output Load Circuit
D C C H A R A C T E R I S T I C S I (TA= - 40° C to 85° C )
Parameter
Power Supply Voltage
Input leakage current
Output leakage current
Output high voltage
Output low voltage
Symbol
V DD
IL
IO
VOH
VOL
Min.
3.0
-1
-1
2.4
-
Max
3.6
1
1
-
0.4
Unit
V
uA
uA
V
V
Note :
1.V DD (min) is 3.15V when HY57V161610DTC-7I operates at C A S latency=2 and tCK2=8.9ns.
2 . V IN = 0 t o 3 . 6 V , A l l o t h e r p i n s a r e n o t u n d e r t e s t = 0 V
3.D OUT is disabled, V OUT=0 to 3.6V
Note
1
2
3
IO H = - 4 m A
IOL = + 4 m A
Rev. 0.2/Aug.01
5
5 Page 
PACKAGE INFORMATION
400mil 50pin Thin Small Outline Package (TC)
1Mx16 Synchronous DRAM
HY57V161610D
UNIT : INCH (mm)
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
5 0 pin TSOP-II
400mil x 825mil
0.8mm pin pitch
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
Rev. 0.2/Aug.01
11
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| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet HY57V161610DTC-6I.PDF ] | |
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