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PDF HY51V65163HGT-45 Data sheet ( Hoja de datos )
| Número de pieza | HY51V65163HGT-45 | |
| Descripción | 4M x 16Bit EDO DRAM | |
| Fabricantes | Hynix Semiconductor | |
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HY51V(S)65163HG/HGL
4M x 16Bit EDO DRAM
PRELIMINARY
DESCRIPTION
This familiy is a 64Mbit dynamic RAM organized 4,194,304 x 16bit configuration with Extended Data Out
mode CMOS DRAMs. Extended data out mode is a kind of page mode which is useful for the read opera-
tion. The advanced circuit and process allow this device to achieve high performance and low power dissi-
pation. Features are access time(45ns or 50ns) and refresh cycle(4K ref ) and power consumption (Normal
or low power with self refresh).
Advanced CMOS process as well as circuit techniques for wide operating margins allow this device to
achieve high speed access and high reliability
FEATURES
• Extended data out operation
• Read-modify-write capability
• Multi-bit parallel test capability
• LVTTL(3.3V) compatible inputs and outputs
• /RAS only, CAS-before-/RAS, Hidden and self
refresh(L-version) capability
• JEDEC standard pinout
50pin plastic SOJ/TSOP-II(400mil)
• Single power supply of 3.3V +/- 10%
• Battery back up operation(L-version)
• Fast access time and cycle time
Part No
HY51V(S)65163HG/HGL-45
HY51V(S)65163HG/HGL-5
HY51V(S)65163HG/HGL-6
tRAC
45ns
50ns
60ns
tAA
23ns
25ns
30ns
tCAC
12ns
13ns
15ns
tRC
74ns
84ns
104ns
tHPC
17ns
20ns
25ns
• Power dissipation
Active
Standby
45ns
50ns
60ns
468mW
432mW
396mW
1.8mW(CMOS level Max)
0.72mW (L-version : Max)
ODERING INFORMATION
• Refresh cycle
Part No
Ref Normal
HY51V65163HG*
4K Ref 64ms
HY51V65163HGL*
4K Ref
* : /RAS only, CBR and hidden refresh
L-part
128ms
Part Number
HY51V(S)65163HG/HG(L)J-45
HY51V(S)65163HG/HG(L)J-5
HY51V(S)65163HG/HG(L)J-6
HY51V(S)65163HG/HG(L)T-45
HY51V(S)65163HG/HG(L)T-5
HY51V(S)65163HG/HG(L)T-6
(S) : Self refresh,
(L) : Low power
Access Time
45ns
50ns
60ns
45ns
50ns
60ns
Package
400mil 50pin SOJ
400mil 50pin TSOP-II
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.0.1/Apr.01
1 page  
HY51V(S)65163HG/HGL
CAPACITANCE (Vcc=3.3V +/-10%, TA=25°C)
Parameter
Symbol
Min.
Max
Unit
Input capacitance (Address)
Input capacitance (Clocks)
Output capacitance (Data-in, Data-out)
CI1
CI2
CI/O
-
-
-
5 pF
5 pF
7 pF
Note : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. /RAS, /UCAS and /LCAS = VIH to disable Dout
Note
1
1
1, 2
AC CHARACTERISTICS (Vcc=3.3V +/-10%, TA=0~70C, Note 1, 2, 19,20)
Test Condition
• Input rise and fall times = 2ns
• Input level : VIL/VIH = 0.0 / 0.3V
• Input timing reference level : VIL/VIH = 0.8/2.0V
• Output timing reference level :
VOL/VOH=0.8/0.2V
• Output load : 1 TTL gate + CL (100pF)
including scope and jig
Read, Write, Read-modify-Write and Refresh Cycles
Parameter
Random read or write cycle time
/RAS precharge time
/CAS precharge time
/RAS pulse width
/CAS pulse width
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
/RAS to /CAS delay time
/RAS to Column address delay time
/RAS hold time
/CAS hold time
/CAS to /RAS precharge time
Symbol
tRC
tRP
tCP
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
-45
Min Max
74 -
25 -
7-
45 10,000
7 10,000
0-
7-
0-
7-
11 33
9 22
12 -
38 -
5-
-50
Min Max
84 -
30 -
8-
50 10,000
8 10,000
0-
8-
0-
8-
12 37
10 25
13 -
40 -
5-
-60
Min Max
Unit
104 - ns
40 - ns
10 - ns
60 10,000 ns
10 10,000 ns
0 - ns
10 - ns
0 - ns
10 - ns
14 45 ns
12 30 ns
15 - ns
42 - ns
5 - ns
Note
24
21
21
3
4
22
Rev.0.1/Apr.01
5
5 Page 
PACKAGE INFORMATION
400mil 50pin TSOP- II Dimension
20.95 MIN
21.35 MAX
HY51V(S)65163HG/HGL
0 ~ 5 deg.
0.40 MIN
0.60 MAX
Unit: mm
1.15 MAX
0.80
0.145 0.05
0.125 0.04
0.30 0.10
0.28 0.08
0.80
0.10
0.08 MIN
0.18 MAX
Dimension including the plating thickness
Base material dimension
Rev.0.1/Apr.01
11
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