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HY29LV800T-55I fiches techniques PDF

Hynix Semiconductor - 8 Mbit (1M x 8/512K x 16) Low Voltage Flash Memory

Numéro de référence HY29LV800T-55I
Description 8 Mbit (1M x 8/512K x 16) Low Voltage Flash Memory
Fabricant Hynix Semiconductor 
Logo Hynix Semiconductor 





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HY29LV800T-55I fiche technique
HY29LV800
8 Mbit (1M x 8/512K x 16) Low Voltage Flash Memory
KEY FEATURES
n Single Power Supply Operation
– Read, program and erase operations from
2.7 to 3.6 volts
– Ideal for battery-powered applications
n High Performance
– 70 and 90 ns access time versions for full
voltage range operation
– 55 ns access time version for operation
from 3.0 to 3.6 volts
n Ultra-low Power Consumption (Typical
Values)
– Automatic sleep mode current: 0.2 µA
– Standby mode current: 0.2 µA
– Read current: 7 mA (at 5 Mhz)
– Program/erase current: 15 mA
n Flexible Sector Architecture:
– One 16 KB, two 8 KB, one 32 KB and
fifteen 64 KB sectors in byte mode
– One 8 KW, two 4 KW, one 16 KW and
fifteen 32 KW sectors in word mode
– Top or bottom boot block configurations
available
n Sector Protection
– Allows locking of a sector or sectors to
prevent program or erase operations
within that sector
– Sectors lockable in-system or via
programming equipment
– Temporary Sector Unprotect allows
changes in locked sectors (requires high
voltage on RESET# pin)
n Fast Program and Erase Times
– Sector erase time: 0.5 sec typical for each
sector
– Chip erase time: 10 sec typical
– Byte program time: 9 µs typical
– Word program time: 11 µs typical
n Unlock Bypass Program Command
– Reduces programming time when issuing
multiple program command sequences
n Automatic Erase Algorithm Preprograms
and Erases Any Combination of Sectors
or the Entire Chip
n Automatic Program Algorithm Writes and
Verifies Data at Specified Addresses
n Minimum 100,000 Write Cycles per Sector
n Compatible With JEDEC standards
Pinout and software compatible with
single-power supply Flash devices
Superior inadvertent write protection
n Data# Polling and Toggle Bits
Provide software confirmation of
completion of program and erase
operations
n Ready/Busy# Pin
Provides hardware confirmation of
completion of program and erase
operations
n Erase Suspend/Erase Resume
Suspends an erase operation to allow
reading data from, or programming data
to, a sector that is not being erased
Erase Resume can then be invoked to
complete suspended erasure
n Hardware Reset Pin (RESET#) Resets the
Device to Reading Array Data
n Space Efficient Packaging
44-pin PSOP, 48-pin TSOP and 48-ball
FBGA packages
LOGIC DIAGRAM
19
A[18:0]
DQ[7:0]
CE#
OE#
WE#
RESET#
BYTE#
DQ[14:8]
DQ[15]/A[-1]
RY/BY#
8
7
Preliminary
Revision 1.0, November 2001

PagesPages 30
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