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PDF HY29LV800T-55 Data sheet ( Hoja de datos )
| Número de pieza | HY29LV800T-55 | |
| Descripción | 8 Mbit (1M x 8/512K x 16) Low Voltage Flash Memory | |
| Fabricantes | Hynix Semiconductor | |
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HY29LV800
8 Mbit (1M x 8/512K x 16) Low Voltage Flash Memory
KEY FEATURES
n Single Power Supply Operation
– Read, program and erase operations from
2.7 to 3.6 volts
– Ideal for battery-powered applications
n High Performance
– 70 and 90 ns access time versions for full
voltage range operation
– 55 ns access time version for operation
from 3.0 to 3.6 volts
n Ultra-low Power Consumption (Typical
Values)
– Automatic sleep mode current: 0.2 µA
– Standby mode current: 0.2 µA
– Read current: 7 mA (at 5 Mhz)
– Program/erase current: 15 mA
n Flexible Sector Architecture:
– One 16 KB, two 8 KB, one 32 KB and
fifteen 64 KB sectors in byte mode
– One 8 KW, two 4 KW, one 16 KW and
fifteen 32 KW sectors in word mode
– Top or bottom boot block configurations
available
n Sector Protection
– Allows locking of a sector or sectors to
prevent program or erase operations
within that sector
– Sectors lockable in-system or via
programming equipment
– Temporary Sector Unprotect allows
changes in locked sectors (requires high
voltage on RESET# pin)
n Fast Program and Erase Times
– Sector erase time: 0.5 sec typical for each
sector
– Chip erase time: 10 sec typical
– Byte program time: 9 µs typical
– Word program time: 11 µs typical
n Unlock Bypass Program Command
– Reduces programming time when issuing
multiple program command sequences
n Automatic Erase Algorithm Preprograms
and Erases Any Combination of Sectors
or the Entire Chip
n Automatic Program Algorithm Writes and
Verifies Data at Specified Addresses
n Minimum 100,000 Write Cycles per Sector
n Compatible With JEDEC standards
– Pinout and software compatible with
single-power supply Flash devices
– Superior inadvertent write protection
n Data# Polling and Toggle Bits
– Provide software confirmation of
completion of program and erase
operations
n Ready/Busy# Pin
– Provides hardware confirmation of
completion of program and erase
operations
n Erase Suspend/Erase Resume
– Suspends an erase operation to allow
reading data from, or programming data
to, a sector that is not being erased
– Erase Resume can then be invoked to
complete suspended erasure
n Hardware Reset Pin (RESET#) Resets the
Device to Reading Array Data
n Space Efficient Packaging
– 44-pin PSOP, 48-pin TSOP and 48-ball
FBGA packages
LOGIC DIAGRAM
19
A[18:0]
DQ[7:0]
CE#
OE#
WE#
RESET#
BYTE#
DQ[14:8]
DQ[15]/A[-1]
RY/BY#
8
7
Preliminary
Revision 1.0, November 2001
1 page  
CONVENTIONS
Unless otherwise noted, a positive logic (active
High) convention is assumed throughout this docu-
ment, whereby the presence at a pin of a higher,
more positive voltage (VIH) causes assertion of the
signal. A ‘#’ symbol following the signal name, e.g.,
RESET#, indicates that the signal is asserted in
the Low state (VIL). See DC specifications for VIH
and VIL values.
MEMORY ARRAY ORGANIZATION
The 8 Mbit Flash memory array is organized into
19 blocks called sectors (S0, S1, . . . , S18). A
sector is the smallest unit that can be erased and
that can be protected to prevent accidental or un-
authorized erasure. See the ‘Bus Operations’ and
‘Command Definitions’ sections of this document
for additional information on these functions.
In the HY29LV800, four of the sectors, which com-
prise the boot block, vary in size from 8 to 32
BUS OPERATIONS
Device bus operations are initiated through the
internal command register, which consists of sets
of latches that store the commands, along with
the address and data information, if any, needed
to execute the specific command. The command
register itself does not occupy any addressable
memory location. The contents of the command
register serve as inputs to an internal state ma-
chine whose outputs control the operation of the
device. Table 3 lists the normal bus operations,
the inputs and control levels they require, and the
resulting outputs. Certain bus operations require
a high voltage on one or more device pins. Those
are described in Table 4.
Read Operation
Data is read from the HY29LV800 by using stan-
dard microprocessor read cycles while placing the
byte or word address on the device’s address in-
puts. The host system must drive the CE# and
OE# pins LOW and drive WE# high for a valid read
operation to take place. The BYTE# pin determines
whether the device outputs array data in words
(DQ[15:0]) or in bytes (DQ[7:0]).
The HY29LV800 is automatically set for reading
array data after device power-up and after a hard-
HY29LV800
Whenever a signal is separated into numbered
bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of
bits may also be shown collectively, e.g., as
DQ[7:0].
The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, .
. . , E, F) indicates a number expressed in hexadeci-
mal notation. The designation 0bXXXX indicates a
number expressed in binary notation (X = 0, 1).
Kbytes (4 to 16 Kwords), while the remaining 15
sectors are uniformly sized at 64 Kbytes (32
Kwords). The boot block can be located at the
bottom of the address range (HY29LV800B) or at
the top of the address range (HY29LV800T).
Tables 1 and 2 define the sector addresses and
corresponding address ranges for the top and bot-
tom boot block versions of the HY29LV800.
ware reset to ensure that no spurious alteration of
the memory content occurs during the power tran-
sition. No command is necessary in this mode to
obtain array data, and the device remains enabled
for read accesses until the command register con-
tents are altered.
This device features an Erase Suspend mode.
While in this mode, the host may read the array
data from any sector of memory that is not marked
for erasure. If the host reads from an address
within an erase-suspended (or erasing) sector, or
while the device is performing a byte or word pro-
gram operation, the device outputs status data
instead of array data. After completing an Auto-
matic Program or Automatic Erase algorithm within
a sector, that sector automatically returns to the
read array data mode. After completing a program-
ming operation in the Erase Suspend mode, the
system may once again read array data with the
same exception noted above.
The host must issue a hardware reset or the soft-
ware reset command to return a sector to the read
array data mode if DQ[5] goes high during a pro-
gram or erase cycle, or to return the device to the
read array data mode while it is in the Electronic
ID mode.
Rev. 1.0/Nov. 01
5
5 Page 
DEVICE COMMANDS
Device operations are initiated by writing desig-
nated address and data command sequences into
the device. Addresses are latched on the falling
edge of WE# or CE#, whichever happens later.
Data is latched on the rising edge of WE# or CE#,
whichever happens first.
A command sequence is composed of one, two
or three of the following sub-segments: an unlock
cycle, a command cycle and a data cycle. Table 5
summarizes the composition of the valid command
sequences implemented in the HY29LV800, and
these sequences are fully described in Table 6 and
in the sections that follow.
Writing incorrect address and data values or writ-
ing them in the improper sequence resets the
HY29LV800 to the Read mode.
Reading Data
The device automatically enters the Read mode
after device power-up, after the RESET# input is
asserted and upon the completion of certain com-
mands. Commands are not required to retrieve
data in this mode. See Read Operation section
for additional information.
Reset Command
Writing the Reset command resets the sectors to
the Read or Erase-Suspend mode. Address bits
are don’t cares for this command.
As described above, a Reset command is not nor-
mally required to begin reading array data. How-
ever, a Reset command must be issued in order
to read array data in the following cases:
n If the device is in the Electronic ID mode, a
Reset command must be written to return to
the Read mode. If the device was in the Erase
Suspend mode when the device entered the
Electronic ID mode, writing the Reset command
returns the device to the Erase Suspend mode.
Note: When in the Electronic ID bus operation mode,
the device returns to the Read mode when V is removed
ID
from the A[9] pin. The Reset command is not required
in this case.
n If DQ[5] (Exceeded Time Limit) goes High dur-
ing a program or erase operation, a Reset com-
mand must be invoked to return the sectors to
HY29LV800
Table 5. Composition of Command Sequences
Command
Sequence
Number of Bus Cycles
Unlock Command Data
Reset
Read
Byte/Word Program
Unlock Bypass
Unlock Bypass
Reset
Unlock Bypass
Byte/Word Program
Chip Erase
0
0
2
2
0
0
4
10
0 Note 1
11
10
11
11
11
Sector Erase
4
1 1 (Note 2)
Erase Suspend
0
1
0
Erase Resume
0
1
0
Electronic ID
2
1 Note 3
Notes:
1. Any number of Flash array read cycles are permitted.
2. Additional data cycles may follow. See text.
3. Any number of Electronic ID read cycles are permitted.
the Read mode (or to the Erase Suspend mode
if the device was in Erase Suspend when the
Program command was issued).
The Reset command may also be used to abort
certain command sequences:
n In a Sector Erase or Chip Erase command se-
quence, the Reset command may be written
at any time before erasing actually begins, in-
cluding, for the Sector Erase command, be-
tween the cycles that specify the sectors to be
erased (see Sector Erase command descrip-
tion). This aborts the command and resets the
device to the Read mode. Once erasure be-
gins, however, the device ignores the Reset
command until the operation is complete.
n In a Program command sequence, the Reset
command may be written between the se-
quence cycles before programming actually be-
gins. This aborts the command and resets the
device to the Read mode, or to the Erase Sus-
pend mode if the Program command sequence
is written while the device is in the Erase Sus-
pend mode. Once programming begins, how-
ever, the device ignores the Reset command
until the operation is complete.
Rev. 1.0/Nov. 01
11
11 Page | ||
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