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PDF HY29F080R90 Data sheet ( Hoja de datos )
| Número de pieza | HY29F080R90 | |
| Descripción | 8 Megabit (1M x 8)/ 5 Volt-only/ Flash Memory | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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HY29F080
8 Megabit (1M x 8), 5 Volt-only, Flash Memory
KEY FEATURES
n 5 Volt Read, Program, and Erase
– Minimizes system-level power
requirements
n High Performance
– Access times as fast as 70 ns
n Low Power Consumption
– 15 mA typical active read current
– 30 mA typical program/erase current
– 5 µA maximum CMOS standby current
n Compatible with JEDEC Standards
– Package, pinout and command-set
compatible with the single-supply Flash
device standard
– Provides superior inadvertent write
protection
n Sector Erase Architecture
– Sixteen equal size sectors of 64K bytes
each
– A command can erase any combination of
sectors
– Supports full chip erase
n Erase Suspend/Resume
– Temporarily suspends a sector erase
operation to allow data to be read from, or
programmed into, any sector not being
erased
GENERAL DESCRIPTION
The HY29F080 is an 8 Megabit, 5 volt-only CMOS
Flash memory organized as 1,048,576 (1M) bytes
of eight-bits each. The device is offered in indus-
try-standard 44-pin PSOP and 40-pin TSOP pack-
ages.
The HY29F080 can be programmed and erased
in-system with a single 5-volt VCC supply. Inter-
nally generated and regulated voltages are pro-
vided for program and erase operations, so that
the device does not require a high voltage power
supply to perform those functions. The device can
also be programmed in standard EPROM pro-
grammers. Access times as fast as 70ns over the
full operating voltage range of 5.0 volts ± 10% are
offered for timing compatibility with the zero wait
state requirements of high speed microprocessors.
n Sector Group Protection
– Sectors may be locked in groups of two to
prevent program or erase operations
within that sector group
n Temporary Sector Unprotect
– Allows changes in locked sectors
(requires high voltage on RESET# pin)
n Internal Erase Algorithm
– Automatically erases a sector, any
combination of sectors, or the entire chip
n Internal Programming Algorithm
– Automatically programs and verifies data
at a specified address
n Fast Program and Erase Times
– Byte programming time: 7 µs typical
– Sector erase time: 1.0 sec typical
– Chip erase time: 16 sec typical
n Data# Polling and Toggle Status Bits
– Provide software confirmation of
completion of program or erase
operations
n Ready/Busy# Pin
– Provides hardware confirmation of
completion of program and erase
operations
n Minimum 100,000 Program/Erase Cycles
n Space Efficient Packaging
– Available in industry-standard 40-pin
TSOP and 44-pin PSOP packages
LOGIC DIAGRAM
20
A[19:0]
RESET#
CE#
OE#
WE#
DQ[7:0]
RY/BY#
8
Revision 6.1, May 2001
1 page  
HY29F080
Table 1. HY29F080 Memory Array Organization
Sec t o r
Sec t o r
Group
Sector/Sector Group Address 1
A[ 19]
A[ 18]
A[ 17]
A[ 16]
S0 0 0 0 0
SG0
S1 0 0 0 1
S2 0 0 1 0
SG1
S3 0 0 1 1
S4
SG2
S5
0
0
10
10
0
1
S6 0 1 1 0
SG3
S7 0 1 1 1
S8 1 0 0 0
SG4
S9 1 0 0 1
S10
SG5
S11
1
1
0
0
10
11
S12 1 1 0 0
SG6
S13 1 1 0 1
S14 1 1 1 0
SG7
S15 1 1 1 1
Notes:
1. A[19:16] are the sector address. A[19:17] are the sector group address.
Address Range A[19:0]
0x00000 - 0x0FFFF
0x10000 - 0x1FFFF
0x20000 - 0x2FFFF
0x30000 - 0x3FFFF
0x40000 - 0x4FFFF
0x50000 - 0x5FFFF
0x60000 - 0x6FFFF
0x70000 - 0x7FFFF
0x80000 - 0x8FFFF
0x90000 - 0x9FFFF
0xA0000 - 0xAFFFF
0xB0000 - 0xBFFFF
0xC0000 - 0xCFFFF
0xD0000 - 0xDFFFF
0xE0000 - 0xEFFFF
0xF0000 - 0xFFFFF
BUS OPERATIONS
Device bus operations are initiated through the
internal command register, which consists of sets
of latches that store the commands, along with
the address and data information, if any, needed
to execute the specific command. The command
register itself does not occupy any addressable
memory location. The contents of the command
register serve as inputs to an internal state ma-
chine whose outputs control the operation of the
device. Table 2 lists the normal bus operations,
the inputs and control levels they require, and the
resulting outputs. Certain bus operations require
a high voltage on one or more device pins. Those
are described in Table 3.
Table 2. HY29F080 Normal Bus Operations 1
Operation
CE#
OE#
WE#
RESET# A[19:0] DQ[7:0]
Read
Write
Output Disable
L LH
L HL
L HH
H AIN DOUT
H AIN DIN
H X High-Z
CE# TTL Standby
H X X H X High-Z
CE# CMOS Standby
Hardware Reset (TTL Standby)
VCC ± 0.3V
X
X
X
X VCC ± 0.3V X High-Z
X L X High-Z
Hardware Reset (CMOS Standby)
X
X X VSS ± 0.5V X
Notes:
1. L = VIL, H = VIH, X = Don’t Care, DOUT = Data Out, DIN = Data In. See DC Characteristics for voltage levels.
High-Z
Rev. 6.1/May 01
5
5 Page 
HY29F080
Rev. 6.1/May 01
11
11 Page | ||
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| PDF Descargar | [ Datasheet HY29F080R90.PDF ] | |
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