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PDF HY29F002TC-70 Data sheet ( Hoja de datos )
| Número de pieza | HY29F002TC-70 | |
| Descripción | 2 Megabit (256K x 8)/ 5 Volt-only/ Flash Memory | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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HY29F002T
2 Megabit (256K x 8), 5 Volt-only, Flash Memory
KEY FEATURES
n 5 Volt Read, Program, and Erase
– Minimizes system-level power requirements
n High Performance
– Access times as fast as 45 ns
n Low Power Consumption
– 20 mA typical active read current
– 30 mA typical program/erase current
– 1 µA typical CMOS standby current
n Compatible with JEDEC Standards
– Package, pinout and command-set
compatible with the single-supply Flash
device standard
– Provides superior inadvertent write
protection
n Sector Erase Architecture
– Boot sector architecture with top boot
block location
– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte
and three 64K byte sectors
– A command can erase any combination of
sectors
– Supports full chip erase
n Erase Suspend/Resume
– Temporarily suspends a sector erase
operation to allow data to be read from, or
programmed into, any sector not being
erased
GENERAL DESCRIPTION
The HY29F002T is an 2 Megabit, 5 volt-only
CMOS Flash memory organized as 262,144
(256K) bytes. The device is offered in industry-
standard 32-pin TSOP and PLCC packages.
The HY29F002T can be programmed and erased
in-system with a single 5-volt VCC supply. Inter-
nally generated and regulated voltages are pro-
vided for program and erase operations, so that
the device does not require a high voltage power
supply to perform those functions. The device can
also be programmed in standard EPROM pro-
grammers. Access times as fast as 55ns over the
full operating voltage range of 5.0 volts ± 10% are
offered for timing compatibility with the zero wait
state requirements of high speed microprocessors.
A 45ns version operating over 5.0 volts ± 5% is
also available. To eliminate bus contention, the
n Sector Protection
– Any combination of sectors may be
locked to prevent program or erase
operations within those sectors
n Temporary Sector Unprotect
– Allows changes in locked sectors
(requires high voltage on RESET# pin)
n Internal Erase Algorithm
– Automatically erases a sector, any
combination of sectors, or the entire chip
n Internal Programming Algorithm
– Automatically programs and verifies data
at a specified address
n Fast Program and Erase Times
– Byte programming time: 7 µs typical
– Sector erase time: 1.0 sec typical
– Chip erase time: 7 sec typical
n Data# Polling and Toggle Status Bits
– Provide software confirmation of
completion of program or erase
operations
n Minimum 100,000 Program/Erase Cycles
n Space Efficient Packaging
– Available in industry-standard 32-pin
TSOP and PLCC packages
LOGIC DIAGRAM
18
A[17:0]
RESET#
CE#
OE#
WE#
DQ[7:0]
8
Revision 4.1, May 2001
1 page  
HY29F002T
Table 2. HY29F002T Normal Bus Operations 1
Operation
CE#
OE#
WE#
RESET# A[17:0] DQ[7:0]
Read
Write
Output Disable
L LH
L HL
L HH
H AIN DOUT
H AIN DIN
H X High-Z
CE# TTL Standby
H X X H X High-Z
CE# CMOS Standby
Hardware Reset (TTL Standby)
VCC ± 0.5V
X
X
X
X VCC ± 0.5V X High-Z
X L X High-Z
Hardware Reset (CMOS Standby)
X
X X VSS ± 0.5V X High-Z
Notes:
1. L = VIL, H = VIH, X = Don’t Care, DOUT = Data Out, DIN = Data In. See DC Characteristics for voltage levels.
BUS OPERATIONS
Device bus operations are initiated through the
internal command register, which consists of sets
of latches that store the commands, along with
the address and data information, if any, needed
to execute the specific command. The command
register itself does not occupy any addressable
memory location. The contents of the command
register serve as inputs to an internal state ma-
chine whose outputs control the operation of the
device. Table 2 lists the normal bus operations,
the inputs and control levels they require, and the
resulting outputs. Certain bus operations require
a high voltage on one or more device pins. Those
are described in Table 3.
Read Operation
Data is read from the HY29F002T by using stan-
dard microprocessor read cycles while placing the
address of the byte to be read on the device’s
address inputs, A[17:0]. As shown in Table 2, the
host system must drive the CE# and OE# inputs
Low and drive WE# High for a valid read opera-
tion to take place. The device outputs the speci-
fied array data on DQ[7:0].
The HY29F002T is automatically set for reading
array data after device power-up and after a hard-
ware reset to ensure that no spurious alteration of
the memory content occurs during the power tran-
sition. No command is necessary in this mode to
obtain array data, and the device remains enabled
for read accesses until the command register con-
tents are altered.
data from or program data into any sector of
memory that is not marked for erasure. If the host
attempts to read from an address within an erase-
suspended sector, or while the device is perform-
ing an erase or byte program operation, the de-
vice outputs status data instead of array data. After
completing a programming operation in the Erase
Suspend mode, the system may once again read
array data with the same exceptions noted above.
After completing an internal program or internal
erase algorithm, the HY29F002T automatically re-
turns to the read array data mode.
The host must issue a hardware reset or the soft-
ware reset command (see Command Definitions)
to return a sector to the read array data mode if
DQ[5] goes high during a program or erase cycle,
or to return the device to the read array data mode
while it is in the Electronic ID mode.
Write Operation
Certain operations, including programming data
and erasing sectors of memory, require the host
to write a command or command sequence to the
HY29F002T. Writes to the device are performed
by placing the byte address on the device’s ad-
dress inputs while the data to be written is input
on DQ[7:0]. The host system must drive the CE#
and WE# pins Low and drive OE# High for a valid
write operation to take place. All addresses are
latched on the falling edge of WE# or CE#, which-
ever happens later. All data is latched on the ris-
ing edge of WE# or CE#, whichever happens first.
This device features an Erase Suspend mode.
While in this mode, the host may read the array
Rev. 4.1/May 01
5
5 Page 
HY29F002T
Rev. 4.1/May 01
11
11 Page | ||
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