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PDF 5962F9670401VXC Data sheet ( Hoja de datos )
| Número de pieza | 5962F9670401VXC | |
| Descripción | Radiation Hardened Dual J-K Flip-Flop | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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ACS112MS
January 1996
Radiation Hardened
Dual J-K Flip-Flop
Features
Pinouts
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96704 and Intersil’sIntersil QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day
(Typ)
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg
• Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability . . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC
16 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835, DESIGNATOR CDIP2-T16,
LEAD FINISH C
TOP VIEW
CP1 1
K1 2
J1 3
S1 4
Q1 5
Q1 6
Q2 7
GND 8
16 VCC
15 R1
14 R2
13 CP2
12 K2
11 J2
10 S2
9 Q2
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current ≤ 1µA at VOL, VOH
• Fast Propagation Delay . . . . . . . . . . . . . . . . 21ns (Max), 14ns (Typ)
Description
The Intersil ACS112MS is a Radiation Hardened Dual J-K Flip-Flop with
Set and Reset. The output change states on the negative transition of
the clock (CP1N or CP2N).
16 PIN CERAMIC FLATPACK
MIL-STD-1835, DESIGNATOR CDFP4-F16,
LEAD FINISH C
TOP VIEW
CP1
K1
J1
S1
Q1
Q1
Q2
GND
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VCC
R1
R2
CP2
K2
J2
S2
Q2
The ACS112MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of the radiation hard-
ened, high-speed, CMOS/SOS Logic Family.
The ACS112MS is supplied in a 16 lead Ceramic Flatpack (K suffix) or a
Ceramic Dual-In-Line Package (D suffix).
Ordering Information
PART NUMBER
5962F9670401VEC
5962F9670401VXC
ACS112D/Sample
ACS112K/Sample
ACS112HMSR
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
25oC
25oC
25oC
SCREENING LEVEL
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
PACKAGE
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
Spec Number 518816
File Number 3571.1
1 page | ||
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