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PDF 5962F9563501QYC Data sheet ( Hoja de datos )
| Número de pieza | 5962F9563501QYC | |
| Descripción | Radiation Hardened Real Time Express Microcontroller | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
HS-RTX2010RH
March 2000
File Number 3961.3
Radiation Hardened Real Time Express™
Microcontroller
The HS-RTX2010RH is a radiation-hardened 16-bit
microcontroller with on-chip timers, an interrupt controller, a
multiply-accumulator, and a barrel shifter. It is particularly
well suited for space craft environments where very high
speed control tasks which require arithmetically intensive
calculations, including floating point math to be performed in
hostile space radiation environments.
This processor incorporates two 256-word stacks with
multitasking capabilities, including configurable stack
partitioning and over/underflow control.
Instruction execution times of one or two machine cycles are
achieved by utilizing a stack oriented, multiple bus
architecture. The high performance ASIC Bus, which is
unique to the RTX product, provides for extension of the
microcontroller architecture using off-chip hardware and
application specific I/O devices.
RTX Microcontrollers support the C and Forth programming
languages. The advantages of this product are further
enhanced through third party hardware and software support.
Combined, these features make the HS-RTX2010RH an
extremely powerful processor serving numerous
applications in high performance space systems. The
HS-RTX2010RH has been designed for harsh space
radiation environments and features outstanding Single
Event Upset (SEU) resistance and excellent total dose
response.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95635. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/spacedefense/space.asp
Ordering Information
ORDERING NUMBER
INTERNAL
MKT. NUMBER
TEMP. RANGE
(oC)
5962F9563501QXC HS8-RTX2010RH-8
55 to 125
5962F9563501QYC HS9-RTX2010RH-8
55 to 125
5962F9563501V9A HS0-RTX2010RH-Q
25
5962F9563501VXC HS8-RTX2010RH-Q
55 to 125
5962F9563501VYC HS9-RTX2010RH-Q
55 to 125
HS8-RTX2010RH/Proto HS8-RTX2010RH/Proto 55 to 125
HS9-RTX2010RH/Proto HS9-RTX2010RH/Proto 55 to 125
Features
• Electrically Screened to SMD # 5962-95635
• QML Qualified per MIL-PRF-38535 Requirements
• Fast 125ns Machine Cycle
• 1.2µM TSOS4 CMOS/SOS Process
• Total Dose Capability . . . . . . . . . . . . . . . . . . 300KRad(Si)
• Single Event Upset Critical LET . . . . . . . >120MeV/mg/cm2
• Single Event Upset Error Rate . . . . <1 x 10-10 Errors/Bit-Day
(Note)
• -55oC - 125oC, 5V ±10% Operation
• Single Cycle Instruction Execution
• Fast Arithmetic Operations
- Single Cycle 16-Bit Multiply
- Single Cycle 16-Bit Multiply Accumulate
- Single Cycle 32-Bit Barrel Shift
- Hardware Floating Point Support
• C Software Development Environment
• Direct Execution of Fourth Language
• Single Cycle Subroutine Call/Return
• Four Cycle Interrupt Latency
• On-Chip Interrupt Controller
• Three On-Chip 16-Bit Timer/Counters
• Two On-Chip 256 Word Stacks
• ASIC Bus™ for Off-Chip Architecture Extension
• 1 Megabyte Total Address Space
• Word and Byte Memory Access
• Fully Static Design - DC to 8MHz Operation
• 84 Lead Quad Flat Package or 85 Pin Grid Array
• Third Party Software and Hardware Development Systems
NOTE: Single Event Upset error rates are Adams 10% worst case
environment under worst case conditions for upset.
Applications
• Space Systems Embedded Control
• Digital Filtering
• Image Processing
• Scientific Instrumentation
• Optical Systems
• Control Systems
• Attitude/Orbital Control
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 2000
Real Time Express™, RTX™, and ASIC Bus™ are trademarks of Intersil Corporation.
1 page  
HS-RTX2010RH
Input Signal, Bus, and Power Connection Descriptions (Continued)
SIGNAL
CQFP
LEAD
DESCRIPTION
EI2, EI1
8, 7 EXTERNAL INTERRUPTS 2, 1: Active HIGH level-sensitive inputs to the Interrupt Controller. Sampled on the rising
edge of PCLK. See Timing Diagrams for detail.
EI5-EI3
11-9
EXTERNAL INTERRUPTS 5, 4, 3: Dual purpose inputs; active HIGH level-sensitive Interrupt Controller inputs;
active HIGH edge-sensitive Timer/Counter inputs. As interrupt inputs, they are sampled on the rising edge of PCLK.
See Timing Diagrams for detail.
NMI 4 NON-MASKABLE INTERRUPT: Active HIGH edge-sensitive Interrupt Controller input capable of interrupting any
processor cycle when NMI is set to Mode 0. See the Interrupt Suppression and Interrupt Controller Sections.
INTSUP
5 INTERRUPT SUPPRESS: A HIGH on this pin inhibits all maskable interrupts, internal and external.
ADDRESS BUSES (OUTPUTS)
GA02
1 ASIC ADDRESS: 3-bit ASIC Address Bus, which carries address information for external ASIC devices.
GA01
84
GA00
83
MA19-MA14
56-51 MEMORY ADDRESS: 19-bit Memory Address Bus, which carries address information for Main Memory.
MA13-MA09
49-45
MA08-MA01
43-36
DATA BUSES (I/O)
GD15-GD13
17-19 ASIC DATA: 16-bit bidirectional external ASIC Data Bus, which carries data to and from off-chip I/O devices.
GD12-GD07
21-26
GD06-GD03
28-31
GD02-GD00
33-35
MD15
82 MEMORY DATA: 16-bit bidirectional Memory Data Bus, which carries data to and from Main Memory.
MD14-MD08
80-74
MD07-MD05
72-70
MD04-MD00
68-64
POWER CONNECTIONS
VDD
6, 27, Power supply +5V connections. A 0.1µF, low impedance decoupling capacitor should be placed between VDD and
50, 73 GND. This should be located as close to the RTX package as possible.
GND
20, 32,
44, 57,
69, 81
Power supply ground return connections.
TYPICAL
CLOCK OR 4.0V
STROBE 0.5V
tPULSE WIDTH
tPULSE WIDTH
2.25V
2.25V 2.25V
tSETUP tHOLD
TYPICAL 4.0V
INPUT 0.5V
TYPICAL
OUTPUT
TYPICAL
DATA
OUTPUT
2.25V
tDELAY
2.25V
tDELAY
tVALID
2.25V
tHOLD
2.25V
2.75V 2.75V
1.75V 1.75V
FIGURE 1. AC DRIVE AND MEASURE POINTS - CLK INPUT
5
5 Page 
HS-RTX2010RH
PCLK
EXECUTION SEQUENCE WITH NO MEMORY DATA ACCESS:
BEGIN
FIRST
CLOCK
CYCLE
CONCURRENT
OPERATIONS
END OF
FIRST
CLOCK
CYCLE
BEGIN
SECOND
CLOCK
CYCLE
INSTRUCTION
LATCHES INTO
IR
PERFORM INTERNAL OPERATIONS AND
ALU OPERATIONS, AS REQUIRED
ADDRESS OF
NEXT
INSTRUCTION
IS PLACED ONTO
MA19-MA01
BUS
FETCH
ASIC BUS OPERATIONS
EXECUTION SEQUENCE WITH MEMORY DATA ACCESS:
BEGIN
FIRST
CLOCK
CYCLE
END OF
FIRST
CLOCK
CYCLE
BEGIN
SECOND
CLOCK
CYCLE
CONCURRENT
OPERATIONS
END OF
SECOND
CLOCK
CYCLE
INSTRUCTION
LATCHES
INTO
IR
ADDRESS OF
MEMORY
LOCATION
IS PLACED ONTO
MA19-MA01
BUS
READ OR WRITE
MEMORY DATA
PERFORM ALU OPERATIONS
PLACE ADDRESS OF
NEXT INSTRUCTION
ONTO MA19-MA01
FETCH NEXT
INSTRUCTION
FIGURE 10. INSTRUCTION EXECUTION SEQUENCE
RTX Data Buses and Address Buses
The RTX core bus architecture provides for unidirectional
data paths and simultaneous operation of some data buses.
This parallelism allows for maximum efficiency of data flow
internal to the core.
Addresses for accessing external (off-chip) memory or
ASIC devices are output via either the Memory Data Bus
(MA19-MA01) or the ASIC Address Bus (GA02-GA00). See
Table 3. External data is transferred by the ASIC Data Bus
(GD15-GD00) and the Memory Data Bus (MD15-MD00),
both of which are bidirectional.
RTX Internal Registers
The core of the HS-RTX2010RH is a macrocell available
through the Intersil Standard Cell Library. This core contains
eight 16-bit internal registers, which may be accessed
implicitly or explicitly, depending upon the register accessed
and the function being performed.
TOP : The Top Register contains the top element of the
Parameter Stack++. TOP is the implicit data source or
destination for certain instructions, and has no ASIC address
assignment. The contents of this register may be directed to
any I/O device or to any processor register except the
Instruction Register. TOP is also the T input to the ALU.
Input to TOP must come through the ALU. This register
also holds the most significant 16 bits of 32-bit products and
32-bit dividends.
NEXT: The Next Register holds the second element of the
Parameter Stack. EXT is the implicit data source or
destination for certain instructions, and has no ASIC address
assignment. During a stack “push”, the contents of NEXT
are transferred to stack memory, and the contents of TOP
are put into NEXT. This register is used to hold the least
significant 16 bits of 32-bit products. Memory data is
accessed through NEXT, as described in the Memory
Access section of this document.
IR : The Instruction Register is actually a latch which
contains the instruction currently being executed, and has no
ASIC address assignment. In certain instructions, an
operand can be embedded in the instruction code, making
IR the implicit source for that operand (as in the case of
short literals). Input to this register comes from Main
Memory (see Tables 6 thru 22 for code information).
CR : The Configuration Register is used to indicate and
control the current status/setup of the RTX microcontroller,
through the bit assignments shown in Figure 11. This
register is accessed explicitly through read and write
operations, which cause interrupts to be suppressed for one
cycle, guaranteeing that the next instruction will be
performed before an Interrupt Acknowledge cycle is allowed
to be performed.
11
11 Page | ||
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