5962-9319502MYA Datasheet PDF - National Semiconductor
| Part Number | 5962-9319502MYA | |
| Description | 12-Bit Sign Data Acquisition System with Self-Calibration | |
| Manufacturers | National Semiconductor | |
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July 1999
LM12454/LM12458/LM12H458
12-Bit + Sign Data Acquisition System with
Self-Calibration
General Description
The LM12454, LM12458, and LM12H458 are highly inte-
grated Data Acquisition Systems. Operating on just 5V, they
combine a fully-differential self-calibrating (correcting linear-
ity and zero errors) 13-bit (12-bit + sign) analog-to-digital
converter (ADC) and sample-and-hold (S/H) with extensive
analog functions and digital functionality. Up to 32 consecu-
tive conversions, using two’s complement format, can be
stored in an internal 32-word (16-bit wide) FIFO data buffer.
An internal 8-word RAM can store the conversion sequence
for up to eight acquisitions through the LM12(H)458’s
eight-input multiplexer. The LM12454 has a four-channel
multiplexer, a differential multiplexer output, and a differential
S/H input. The LM12454 and LM12(H)458 can also operate
with 8-bit + sign resolution and in a supervisory “watchdog”
mode that compares an input signal against two program-
mable limits.
Programmable acquisition times and conversion rates are
possible through the use of internal clock-driven timers. The
reference voltage input can be externally generated for ab-
solute or ratiometric operation or can be derived using the in-
ternal 2.5V bandgap reference.
All registers, RAM, and FIFO are directly addressable
through the high speed microprocessor interface to either an
8-bit or 16-bit databus. The LM12454 and LM12(H)458 in-
clude a direct memory access (DMA) interface for
high-speed conversion data transfer.
An evaluation/interface board is available. Order num-
ber LM12458EVAL.
Additional applications information can be found in applica-
tions notes AN-906, AN-947 and AN-949.
Key Specifications
(fCLK = 5 MHz; 8 MHz, H)
j Resolution
12-bit + sign or 8-bit + sign
j 13-bit conversion time
8.8 µs, 5.5 µs (H) (max)
j 9-bit conversion time
4.2 µs, 2.6 µs (H) (max)
j 13-bit Through-put rate
88k samples/s (min),
140k samples/s (H) (min)
j Comparison time
(“watchdog” mode)
2.2 µs (max),
1.4 µs (H) (max)
j ILE
±1 LSB (max)
j VIN range
j Power dissipation
GND to VA+
30 mW, 34 mW (H) (max)
j Stand-by mode
50 µW (typ)
j Single supply
3V to 5.5V
Features
n Three operating modes: 12-bit + sign, 8-bit + sign, and
“watchdog”
n Single-ended or differential inputs
n Built-in Sample-and-Hold and 2.5V bandgap reference
n Instruction RAM and event sequencer
n 8-channel (LM12(H)458), 4-channel (LM12454)
multiplexer
n 32-word conversion FIFO
n Programmable acquisition times and conversion rates
n Self-calibration and diagnostic mode
n 8- or 16-bit wide databus dmicroprocessor or DSP
interface
Applications
n Data Logging
n Instrumentation
n Process Control
n Energy Management
n Inertial Guidance
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
AT® is a registered trademark of International Business Machines Corporation.
© 1999 National Semiconductor Corporation DS011264
www.national.com
|
| |
 
Converter Characteristics (Notes 6, 7, 8, 9, 19) (Continued)
The following specifications apply to
12-bit + sign conversion mode, fCLK
=the8.0LMM1H2z45(L4M, L1M2H12445588) ,oar nfCdLLKM=152.H04M58Hzfo(rLVMA1+2=45V4D/8+),
= 5V,
RS =
VREF+ = 5V,
25Ω, source
VREF− = 0V,
impedance for
VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless
otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C.
Symbol
Parameter
Conditions
Typical Limits
Unit
(Note 10) (Note 11) (Limit)
8-Bit + Sign and “Watchdog” Mode
±1/8
LSB
DC Common Mode Error
Multiplexer Channel-to-Channel
±0.05
LSB
Matching
VIN+
Non-Inverting Input Range
VIN−
Inverting Input Range
VIN+ − VIN− Differential Input Voltage Range
Common Mode Input Voltage Range
GND
VA+
GND
VA+
−VA+
VA+
GND
V (min)
V (max)
V (min)
V (max)
V (min)
V (max)
V (min)
PSS
Power Supply
Sensitivity
(Note 15)
Zero Error
Full-Scale Error
Linearity Error
VA+ = VD+ = 5V ±10%
VREF+ = 4.5V, VREF− = GND
±0.2
±0.4
±0.2
VA+
±1.75
±2
V (max)
LSB (max)
LSB (max)
LSB
CREF
CIN
VREF+/VREF− Input Capacitance
Selected Multiplexer Channel Input
Capacitance
85 pF
75 pF
Converter AC Characteristics (Notes 6, 7, 8, 9, 19)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ = VD+ = 5V, VREF+ = 5V, VREF− = 0V,
12-bit + sign conversion mode, fCLK = 8.0 MHz (LM12H458) or fCLK = 5.0 MHz (LM12454/8), RS = 25Ω, source impedance for
VREF+ and VREF− ≤
otherwise specified.
25Ω, fully-differential input with
Boldface limits apply for TA
fixed 2.5V common-mode voltage, and
= TJ = TMIN to TMAX; all other limits TA
minimum acquisition
= TJ = 25˚C.
time
unless
Symbol
Parameter
Conditions
Typical
Limits
Unit
(Note 10)
(Note 11)
(Limit)
Clock Duty Cycle
50 %
40 % (min)
60 %
(max)
tC Conversion Time
13-Bit Resolution,
Sequencer State S5 (Figure 15)
44 (tCLK)
44 (tCLK) + 50 ns
(max)
9-Bit Resolution,
Sequencer State S5 (Figure 15)
21 (tCLK)
21 (tCLK) + 50 ns
(max)
tA Acquisition Time
Sequencer State S7 (Figure 15)
Built-in minimum for 13-Bits
9 (tCLK)
9 (tCLK) + 50 ns
(max)
Built-in minimum for 9-Bits and
“Watchdog” mode
2 (tCLK)
2 (tCLK) + 50 ns
(max)
tZ Auto-Zero Time
tCAL Full Calibration Time
Throughput Rate
Sequencer State S2 (Figure 15)
Sequencer State S2 (Figure 15)
76 (tCLK)
4944 (tCLK)
89
76 (tCLK) + 50 ns
4944 (tCLK) + 50 ns
88
(max)
(max)
kHz
(Note 18)
LM12H458
142 140 (min)
tWD
“Watchdog” Mode Comparison
Sequencer States S6, S4,
Time
and S5 (Figure 15)
11 (tCLK)
11 (tCLK) + 50 ns
(max)
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