EBS52UC8APSA-7AL Datasheet PDF - Elpida Memory
| Part Number | EBS52UC8APSA-7AL | |
| Description | 512MB SDRAM S.O.DIMM | |
| Manufacturers | Elpida Memory | |
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DATA SHEET
512MB SDRAM S.O.DIMM
EBS52UC8APSA (64M words × 64 bits, 2 bank)
Description
The EBS52UC8APSA is 64M words × 64 bits, 2 banks
Synchronous Dynamic RAM Small Outline Dual In-line
Memory Module (S.O.DIMM), mounted 16 pieces of
256M bits SDRAM sealed in µBGA package. This
module provides high density and large quantities of
memory in a small space without utilizing the surface
mounting technology. Decoupling capacitors are
mounted on power supply line for noise reduction.
Note : Do not push the cover or drop the modules in
order to protect from mechanical defects, which
would be electrical defects.
Features
• Fully compatible with 8 bytes S.O.DIMM: JEDEC
standard outline
• 144-pin socket type small outline dual in line memory
module (S.O.DIMM)
PCB height: 31.75mm (1.25inch )
Lead pitch: 0.80mm
• 3.3V power supply
• Clock frequency: 133MHz (max.)
• LVTTL interface
• Data bus width: × 64 non-ECC
• Single pulsed /RAS
• 4 Banks can operates simultaneously and
independently
• Burst read/write operation and burst read/single write
operation capability
• Programmable burst length (BL): 1, 2, 4, 8, Full page
• 2 variations of burst sequence
Sequential
Interleave
• Programmable /CAS latency (CL): 2, 3
• Byte control by DQMB
• Refresh cycles: 8192 refresh cycles/64ms
• 2 variations of refresh
Auto refresh
Self refresh
Document No. E0240E20 (Ver. 2.0)
Date Published May 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2001-2002
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EBS52UC8APSA
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
28 Row active to row active min
29
/RAS to /CAS delay min
(-7A/7AL)
(-75/75L)
0 0 0 0 1 1 1 1 0FH
0 0 0 0 1 1 1 1 0FH
0 0 0 1 0 1 0 0 14H
30 Minimum /RAS pulse width
0 0 1 0 1 1 0 1 2DH
31
Density of each bank on module
0 1 0 0 0 0 0 0 40H
32
Address and command signal input
setup time
0
0
0
1
0
1
0
1
15H
33
Address and command signal input
hold time
0
0
0
0
1
0
0
0
08H
34 Data signal input setup time
0 0 0 1 0 1 0 1 15H
35 Data signal input hold time
0 0 0 0 1 0 0 0 08H
36 to 61 Superset information
0 0 0 0 0 0 0 0 00H
62 SPD data revision code
63
Checksum for Bytes 0 to 62
(-7A/7AL)
(-75/75L)
0 0 0 1 0 0 1 0 12H
1 0 0 1 0 0 1 0 92H
1 1 0 1 0 0 1 1 D3H
64 to 65 Manufacturer’s JEDEC ID code
0 1 1 1 1 1 1 1 7FH
66
Manufacturer’s JEDEC ID code
1 1 1 1 1 1 1 0 FEH
67 to 71 Manufacturer’s JEDEC ID code
0 0 0 0 0 0 0 0 00H
72 Manufacturing location
73 to 90 Manufacturer’s part number
91 to 92 Revision code
93 to 94 Manufacturing date
95 to 98 Assembly serial number
99 to 125 Manufacturer specific data
126
Reserved (Intel specification
frequency)
0 1 1 0 0 1 0 0 64H
127
Reserved (Intel specification /CAS#
latency support)
1
1
0
0
0
1
1
1
C7H
Comments
15ns
15ns
20ns
45ns
256MB
1.5ns
0.8ns
1.5ns
0.8ns
1.2
Continuation code
Elpida Memory
100MHz
Data Sheet E0240E20 (Ver. 2.0)
5
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for EBS52UC8APSA-7AL electronic component. |
| Information | Total 14 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ EBS52UC8APSA-7AL.PDF Datasheet ] | |
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