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PDF FPD87310 Data sheet ( Hoja de datos )
| Número de pieza | FPD87310 | |
| Descripción | Universal Interface XGA Panel Timing Controller with RSDS (Reduced Swing Differential Signaling) and FPD-Link | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
May 2000
FPD87310
Universal Interface XGA Panel Timing Controller with
RSDS™ (Reduced Swing Differential Signaling) and
FPD-Link
General Description
The FPD87310 Panel Timing Controller is an integrated
FPD-Link + RSDS + TFT-LCD Timing Controller. It resides
on the Flat Panel Display and provides the interface signal
routing and Timing Control between Graphics or Video Con-
trollers and a TFT-LCD system. FPD-Link, a low power, low
EMI (ElectroMagnetic Interference) interface is used be-
tween this Controller and the Host system.
A RSDS (Reduced Swing Differential Signaling) Column
Driver interface is used between the Timing Controller and
the Column Drivers.
Programmable, General Purpose Outputs provide Row and
Column Driver control. The FPD87310 is configured via
metal mask initialization value or an optional external serial
EEPROM. Reserved space in the EEPROM is available for
display identification information. The system can access the
EEPROM to read the display identification data or program
initialization values used by the FPD87310.
This single 9-bit+CLK differential bus conveys the 18 bits
color data for XGA panels at 130 Mb/s when using VESA 60
Hz standard timing.
Features
n RSDS (Reduced Swing Differential Signaling) Column
Driver bus for low power and reduced EMI
n Drives RSDS Column Drivers at 130 Mb/s with a 65
MHz clock
n 6- or 8-bit LVDS Video System Interface (FPD-Link)
n 10 General Purpose Outputs for Column/Row Drivers
n Optional EEPROM programming allows fine tuning in
development and production environments
n Selectable dual initialization value sets to share parts for
the different model panel module
n Ability to drive XGA/SVGA TFT-LCD Systems
n Narrow 9-bit+CLK differential Column Driver Bus
minimizes width of Source PCB
n CMOS circuitry operates from a 3.3V supply
n Supports Graphics Controllers with spread spectrum
interface featurefor lower EMI
System Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation DS101077
DS101077-1
www.national.com
1 page  
AC Electrical Characteristics (Continued)
FIGURE 6. FPD87310 Power Up Sequence
DS101077-33
5 www.national.com
5 Page 
Programmable Registers
At power-up, data is read from an external EEPROM. If anything other than 00H is read back on the first EEPROM access (in-
dicating EEPROM not present), the internal default values are used.
Pull-Up must be used on EE_SD pin if external EEPROM is not used.
The following parameters are initialized at power up.
Control
Registers
Output Format
Control
(16 bits)
Input Format
Control
(8 bits)
Horizontal
Backporch
(11 bits)
Vertical
Backporch
(11 bits)
TABLE 1. FPD87310 Programmable Register Definition
EEPROM
Address
082H, 081H
085H
087H, 086H
The CONTROL REGISTER provide more setting information to the
input and output interfaces.
[2:0] Reserved
[3] Output Data Inversion
“0” - Data inversion is Disabled
“1” - Data inversion is Enabled
[4] Output Data Inversion/Polarity
“0” - Data Inversion when GPO[0] is “0”
“1” - Data inversion when GPO[0] is “1”
[7:5] Reserved
[11:8] RSDS output setup/hold time control
[13:12] Unused Pixels
“00” - no unconnected pixels at beginning of first CD
“01” - 1 unconnected pixels at beginning of first CD
“10” - 2 unconnected pixels at beginning of first CD
“11” - 3 unconnected pixels at beginning of first CD
[15:14] Reserved
[1:0] Reserved
[2] Reserved
[3] Frame Rate Control (8 bits only)
“0” - Enable Frame Rate Control
“1” - Disable Frame Rate Control (Truncate LSBs)
[4] 8/6 Bits Video
“0” - 6 Bits Video
“1” - 8 Bits Video
[5] Reserved
[7:6] Black or White data Generation
“00” - No data manipulation is performed
“10” - Data goes to “0” when GPO[9] is “0”
“11” - Data goes to “1” when GPO[9] is “0”
Black data “0” or White data “1” will be output on lines > 768.
GPO[9] must be programmed to > 768 lines for data to be output.
# of 65 MHz clocks after the falling edge of HYSYNC until start of video.
089H, 088H # of HSYNC from VSYNC falling edge until start of video.
11 www.national.com
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| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet FPD87310.PDF ] | |
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