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PDF FP31QF-PCB2140 Data sheet ( Hoja de datos )

Número de pieza FP31QF-PCB2140
Descripción 2-Watt HFET
Fabricantes ETC 
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No Preview Available ! FP31QF-PCB2140 Hoja de datos, Descripción, Manual

FP31QF
2-Watt HFET
The Communications Edge TM
Product Information
Product Features
Product Description
Functional Diagram
50 – 4000 MHz
18 dB Gain @ 900 MHz
+34 dBm P1dB
+46 dBm Output IP3
High Drain Efficiency
Pb-free 6mm 28-pin QFN package
MTTF > 100 years
Applications
Mobile Infrastructure
CATV / DBS
W-LAN / ISM
RFID
Defense / Homeland Security
Fixed Wireless
The FP31QF is a high performance 2-Watt HFET
(Heterostructure FET) in a low-cost lead-free 28-pin 6x6
mm QFN (Quad Flatpack, No-Lead) surface-mount
package. This device works optimally at a drain bias of
+9 V and 450 mA to achieve +46 dBm output IP3
performance and an output power of +34 dBm at 1-dB
compression.
The device conforms to WJ Communications’ long
history of producing high reliability and quality
components. The FP31QF has an associated MTTF of a
minimum of 100 years at a mounting temperature of
85°C. All devices are 100% RF & DC tested.
The product is targeted for use as driver amplifiers for
wireless infrastructure where high performance and high
efficiency are required.
GND 1
GND 2
GATE /
RF IN
3
GND 4
GND 5
GND 6
GND 7
28 27 26 25 24 23 22
21 GND
20 GND
19
DRAIN /
RF OUT
18 GND
17 GND
16 GND
15 GND
8 9 10 11 12 13 14
Function
Gate /
RF Input
Drain /
RF Output
Ground
Pin No.
3
19
All other pins &
backside copper
Specifications
Typical Performance (4)
DC Parameter
Saturated Drain Current, Idss
Transconductance, Gm
Pinch Off Voltage, Vp (1)
Units
mA
mS
V
Min
Typ
1170
590
-2.0
Max
RF Parameter (2)
Operational Bandwidth
Test Frequency
Small Signal Gain
Maximum Stable Gain
Output P1dB
Output IP3 (3)
Noise Figure
Units
MHz
MHz
dB
dB
dBm
dBm
dB
Min
50
Typ
800
18
24
+34
+46
3.5
Max
4000
1. Pinch-off voltage is measured when Ids = 4.8 mA.
2. Test conditions unless otherwise noted: T = 25ºC, VDS = 9 V, IDQ = 450 mA, in a tuned application
circuit with ZL = ZLOPT, ZS = ZSOPT (optimized for output power).
3. 3OIP measured with two tones at an output power of +18 dBm/tone separated by 1 MHz. The
suppression on the largest IM3 product is used to calculate the 3OIP using a 2:1 rule.
Parameter
Frequency
Gain
S11
S22
Output P1dB
Output IP3 (3)
Noise Figure
IS-95 Channel Power
@ -45 dBc ACPR
W-CDMA Ch. Power
@ -45 dBc ACLR
Drain Voltage (5)
Drain Current (5)
Units
MHz
dB
dB
dB
dBm
dBm
dB
dBm
dBm
V
mA
Typical
915 1960 2140 2450
18 13.5 13 12
-20 -20 -18 -18
-12 -11 -24 -15
+34 +33.8 +33.2 +33.5
+46 +46.8 +46.6 +46.8
3.5 4.5 4.6 4.6
+27.8 +27.3
+25
+9
450
4. Typical parameters represent performance in an application circuit.
5. Empirical measurements showed optimal power performance at a drain voltage = 9 volts at 450 mA.
Because the FP31QF is a discrete device, users can choose their own bias configuration. Performance
may vary from the data shown depending on the biasing conditions. To achieve a minimum 1 million
hours MTTF rating, the biasing condition should maintain a junction temperature below 160° C over all
operating temperatures. This can be approximated by (drain voltage) x (drain current) x 17.5° C/W +
(maximum operating temperature).
Absolute Maximum Rating
Ordering Information
Parameter
Operating Case Temperature
Storage Temperature
DC Power
RF Input Power (continuous)
Drain to Gate Voltage, Vdg
Junction Temperature
Rating
-40 to +85 °C
-55 to +125 °C
7.5 W
6 dB above Input P1dB
+14 V
+220° C
Part No.
FP31QF
FP31QF-F
FP31QF-PCB900
FP31QF-PCB1900
FP31QF-PCB2140
Description
2-Watt HFET
(Leaded QFN Pkg)
2-Watt HFET
(lead-free/RoHS-compliant QFN Pkg)
870 – 960 MHz Application Circuit
1930 – 1990 MHz Application Circuit
2110 – 2170 MHz Application Circuit
Operation of this device above any of these parameters may cause permanent damage.
Specifications and information are subject to change without notice
WJ Communications, Inc Phone 1-800-WJ1-4401 FAX: 408-577-6621 e-mail: [email protected] Web site: www.wj.com
November 2004

1 page




FP31QF-PCB2140 pdf
FP31QF
2-Watt HFET
The Communications Edge TM
Product Information
Application Circuit: 1930 – 1960 MHz (FP31QF-PCB1900)
The application circuit is matched for output power.
Typical RF Performance
Drain Bias = +9 V, Ids = 450 mA, 25°C
Frequency
MHz 1930 1960
S21 – Gain
dB 14 13.8
S11 – Input Return Loss
dB -17 -21
S22 – Output Return Loss dB -11 -11
Output P1dB
dBm +33.5 +33.8
Output IP3
(+18 dBm / tone, 1 MHz spacing)
dBm
+46.8
Noise Figure
dB 4.3 4.5
IS-95 Channel Power
@ -45 dBc ACPR
dBm
+27.3
1990
13.8
-27
-13
+33.8
4.4
C2 C3
Circuit Board Material: .014” FR-4 (εr = 4.6),
4 layers (other layers added for rigidity), .062” total thickness, 1 oz copper
The main microstrip line has a line impedance of 50 .
Ref. Desig.
C1, C4, C8, C10
C2
C3
C6, C11
C7
C12
L1, L2
L3
R1
R2
Q1
C5
Bill of Materials
Value
22 pF
Part style
Chip capacitor
2.2 pF
Chip capacitor
2.0 pF
Chip capacitor
0.018 µF
1000 pF
Chip capacitor
Chip capacitor
0.1 µF
12 nH
Chip capacitor
Wirewound chip inductor
4.7 nH
Multilayer chip inductor
5.1
Chip resistor
51
Chip resistor
FP31QF WJ 2W HFET
Do Not Place
Size
0603
0603
0603
0805
0603
1206
0805
0603
0603
0603
QFN 6x6
The C2 and C3 placements are at silk screen markers, “B” and “3”, respectively.
The via hole spacing along the main microstrip line is .040”.
The distance from the edge of the FP31QF to the closer edge of L3 is .305”.
The transmission line lengths shown in the schematic are from the FP31QF
device edge to the component edge.
P ORT
P =1
Z=50 Ohm
CAP
ID=C1
C=2 2 pF
IND
ID=L3
L =4.7 nH
CA P
ID=C2
C=2.2 pF
CA P
ID=C6
CAP
ID =C7
CA P
ID=C8
C=2 2 pF C =100 0 pF C=1.8e 4 pF
-Vgg Vds=9V @ 450 mA
TLINP
ID =TL1
Z0 =50 Ohm
L =190 mil
Eeff =3 .46
Loss =0
F0 =0 MHz
RES
ID=R2
R=51 Ohm
CAP
ID=C5
C=DNP pF
IND
ID=L1
L =1 2 nH
1
2
RES
ID=R1
R=5 Ohm
SUB CKT
ID=Q1
NET="FP31QF"
IND
ID=L2
L =1 2 nH
TL INP
ID=TL2
Z0 =50 Ohm
L =200 mil
Eeff=3 .46
Loss=0
F0 =0 MHz
CAP
ID=C12
C=1e 5 pF
CAP
ID=C11
C=1.8e 4 pF
CAP
ID =C10
C =2 2 pF
CAP
ID=C4
C=2 2 pF
P ORT
P =2
Z=50 Ohm
CAP
ID=C3
C=2 pF
Specifications and information are subject to change without notice
WJ Communications, Inc Phone 1-800-WJ1-4401 FAX: 408-577-6621 e-mail: [email protected] Web site: www.wj.com
November 2004

5 Page





FP31QF-PCB2140 arduino
FP31QF
2-Watt HFET
The Communications Edge TM
Product Information
Application Note: Constant-Current Active-Biasing
Special attention should be taken to properly bias the FP31QF.
Power supply sequencing is required to prevent the device from
+Vdd
operating at 100% Idss for a prolonged period of time and possibly
causing damage to the device. It is recommended that for the safest
operation, the negative supply be “first on and last off.” With a R1
R2
negative gate voltage present, the drain voltage can then be applied
to the device. The gate voltage can then be adjusted to have the
device be used at the proper quiescent bias condition.
U1
4 Rohm UMT1N 1
C1
.01 µF
An optional active-bias current mirror is recommended for use with
the application circuits shown this datasheet. Generally in a
laboratory environment, the gate voltage is adjusted until the drain
draws the recommended operating current. The gate voltage
required can vary slightly from device to device because of device
pinchoff variation, while also varying slightly over temperature.
R3
3
The active-bias circuit, shown on the right, uses dual PNP transistors
to provide a constant drain current into the FP31QF, while also
eliminating the effects of pinchoff variation. This configuration is
best suited for applications where the intended output power level of
the amplifier is backed off at least 6 dB away from its compression
point. With the implementation of the circuit, lower P1dB values
may be measured for a Class-AB amplifier, where the device will
attempt to source more drain current while the circuit tries to provide
a constant drain current. The circuit should be connected directly in
line with where the voltage supplies would be normally connected
with the amplifier circuit, as shown the diagram. Any required
matching circuitry remains the same, although it is not shown in the
diagram. This recommended active-bias constant-current circuit
adds 7 components to the parts count for implementation, but should
cost only an extra $0.144 to realize ($0.10 for U1, $0.0029 for R1,
R3, R4, R5, $0.024 for R2, and $0.0085 for C1).
25
6
R4
1 k
R5
RF IN
M.N. DUT
RF OUT
M.N.
-Vgg
HFET Application Circuit
Parameter
Pos Supply, Vdd
Neg Supply, Vgg
Vds
Ids
R1
R2*
R3
R4
R5
FP31QF
+9 V
-5 V
+8.75. V
450 mA
62
0.56
2 k
1 k
1 k
Temperature compensation is achieved by tracking the voltage
variation with the temperature of the emitter-to-base junction of the
two PNP transistors. As a 1st order approximation, this is achieved
by using matched transistors with approximately the same Ibe
current. Thus the transistor emitter voltage adjusts the HFET gate
voltage so that the device draws a constant current, regardless of the
temperature. A Rohm dual transistor - UMT1N - is recommended
for cost, minimal board space requirements, and to minimize the
variation between the two transistors. Minimizing the variability
between the base-to-emitter junctions allow more accuracy in setting
the current draw. More details can be found in a separate application
note “Active-bias Constant-current Source Recommended for
HFETs” found on the WJ website.
*R2 should be of size 1206 to dissipate 0.113 Watts.
This should be of 1% tolerance. Two 1.1 resistors in
parallel of size 0805 can also be used.
Specifications and information are subject to change without notice
WJ Communications, Inc Phone 1-800-WJ1-4401 FAX: 408-577-6621 e-mail: [email protected] Web site: www.wj.com
November 2004

11 Page







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