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PDF M28256 Data sheet ( Hoja de datos )
| Número de pieza | M28256 | |
| Descripción | 256 Kbit 32Kb x8 Parallel EEPROM with Software Data Protection | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M28256
256 Kbit (32Kb x8) Parallel EEPROM
with Software Data Protection
FAST ACCESS TIME:
– 90ns at 5V
– 120ns at 3V
SINGLE SUPPLY VOLTAGE:
– 5V ± 10% for M28256
– 2.7V to 3.6V for M28256-xxW
LOW POWER CONSUMPTION
FAST WRITE CYCLE:
– 64 Bytes Page Write Operation
– Byte or Page Write Cycle
ENHANCED END of WRITE DETECTION:
– Data Polling
– Toggle Bit
STATUS REGISTER
HIGH RELIABILITY DOUBLE POLYSILICON,
CMOS TECHNOLOGY:
– Endurance >100,000 Erase/Write Cycles
– Data Retention >10 Years
JEDEC APPROVED BYTEWIDE PIN OUT
ADDRESS and DATA LATCHED ON-CHIP
SOFTWARE DATA PROTECTION
PRELIMINARY DATA
28
1
PDIP28 (BS)
PLCC32 (KA)
28
1
SO28 (MS)
300 mils
TSOP28 (NS)
8 x13.4mm
Figure 1. Logic Diagram
DESCRIPTION
The M28256 and M28256-Ware 32K x8 low power
Parallel EEPROM fabricatedwith STMicroelectron-
ics proprietary double polysilicon CMOS technol-
ogy.
Table 1. Signal Names
A0-A14
Address Input
DQ0-DQ7 Data Input / Output
W Write Enable
E Chip Enable
G Output Enable
VCC Supply Voltage
VSS Ground
VCC
15
A0-A14
8
DQ0-DQ7
W M28256
E
G
VSS
AI01885
January 1999
This is preliminary information on a new product now in developmentor undergoing evaluation . Detail s are subject to change without notice.
1/21
1 page  
M28256
Status Register
The devices provide several Write operation status
flags that can be used to minimize the application
write time. These signals are available on the I/O
port bits during programming cycle only.
Data Polling bit (DQ7). During the internal write
cycle, any attempt to read the last byte written will
produce on DQ7 the complementary value of the
previously latched bit. Once the write cycle is fin-
ished the true logic value appears on DQ7 in the
read cycle.
Toggle bit (DQ6). The devices offer another way
for determining when the internal write cycle is
completed. During the internal Erase/Write cycle,
DQ6 will toggle from ”0” to ”1” and ”1” to ”0” (the
first read value is ”0”) on subsequent attempts to
read any byte of the memory. When the internal
cycle is completed the toggling will stop and the
data read on DQ7-DQ0 is the addressed memory
byte. The device is now accessible for a new Read
or Write operation.
Page Load TimerStatus bit(DQ5). Duringa Page
Write instruction, the devices expect to receive the
stream of data with a minimum period of time
between each data byte. This period of time
(tWHWH) is defined by the on-chip Page Load timer
which running/overflow status is available on DQ5.
DQ5 Low indicates that the timer is running, DQ5
High indicates the time-out after which the internal
write cycle will start.
Figure 4. Status Bit Assignment
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DP TB PLTS X X X X X
DP = Data Polling
TB = Toggle Bit
PLTS = Page Load Timer Status
Software Data Protection
The devices offer a software controlled write pro-
tection facility that allows the user to inhibit all write
modes to the device. This can be useful in protect-
ing the memory from inadvertent write cycles that
may occur due to uncontrolledbus conditions.
The devices are shipped as standardin the ”unpro-
tected” state meaning that the memory contents
can be changed as required by the user. After the
Software Data Protection enable algorithm is is-
sued, the device enters the ”Protect Mode” of
operation where no further write commands have
any effect on the memory contents.
The devices remain in this mode until a valid
Software Data Protection (SDP) disable sequence
is received whereby the device reverts to its ”un-
protected” state. The Software Data Protection is
fully non-volatile and is not changed by power
on/off sequences. To enable the Software Data
Protection (SDP) the device requires the user to
write (with a Page Write addressing three specific
data bytes to three specific memorylocations,each
location in a different page) as per Figure 6. Simi-
larly to disable the Software Data Protection the
user has to write specific data bytes into six differ-
ent locations as per Figure 5 (with a Page Write
adressing different bytes in different pages).
This complexseries ensures that the userwill never
enable or disable the Software Data Protection
accidentally.
To write into the devices when SDP is set, the
sequence shown in Figure 6 must be used. This
sequence provides an unlock key to enable the
write action, and at the same time SDP continues
to be set.
An extension to this is where SDP is required to be
set, and data is to be written.
Using the same sequence as above, the data can
be written and SDP is set at the same time, giving
both these actions in the same Write cycle (tWC).
5/21
5 Page 
M28256
Table 13. Write Mode AC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 2.7V to 3.6V)
Symbol
Alt
Parameter
Test Condition
tAVWL
tAS Address Valid to Write Enable Low
tAVEL
tAS Address Valid to Chip Enable Low
tELWL
tCES Chip Enable Low to Write Enable Low
tGHWL
tOES
Output Enable High to Write Enable
Low
tGHEL
tOES Output Enable High to Chip Enable Low
tWLEL
tWES
Write Enable Low to Chip Enable Low
tWLAX
tAH Write Enable Low to Address Transition
tELAX
tAH Chip Enable Low to Address Transition
tWLDV
tDV Write Enable Low to Input Valid
tELDV
tDV Chip Enable Low to Input Valid
tELEH
tWP Chip Enable Low to Chip Enable High
tWHEH
tCEH Write Enable High to Chip Enable High
tWHGL
tOEH
Write Enable High to Output Enable
Low
tEHGL
tOEH Chip Enable High to Output Enable Low
tEHWH
tWEH
Chip Enable High to Write Enable High
tWHDX
tDH Write Enable High to Input Transition
tEHDX
tDH Chip Enable High to Input Transition
tWHWL
tWPH
Write Enable High to Write Enable Low
tWLWH
tWP Write Enable Low to Write Enable High
tWHWH
tBLC Byte Load Repeat Cycle Time
tWHRH
tWC Write Cycle Time
tEL, tWL
E or W Input Filter Pulse Width
tDVWH
tDS Data Valid before Write Enable High
tDVEH
tDS Data Valid before Chip Enable High
Note: 1. Characterized only but not tested in production.
E = VIL, G = VIH
G = VIH, W = VIL
G = VIH
E = VIL
W = VIL
G = VIH
E = VIL, G = VIH
G = VIH, W = VIL
Note 1
M28256-W
Min Max
0
0
0
Unit
ns
ns
ns
0 ns
0
0
70
70
1
1
100
0
ns
ns
ns
ns
µs
µs
ns
ns
0 ns
0 ns
0 ns
0 ns
0 ns
100 ns
100 ns
0.2 150 µs
5 ms
10 ns
50 ns
50 ns
11/21
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet M28256.PDF ] | |
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