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PDF M27W402-120B6TR Data sheet ( Hoja de datos )
| Número de pieza | M27W402-120B6TR | |
| Descripción | 4 Mbit 256Kb x16 Low Voltage UV EPROM and OTP EPROM | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M27W402
4 Mbit (256Kb x16) Low Voltage UV EPROM and OTP EPROM
s 2.7V to 3.6V SUPPLY VOLTAGE in READ
OPERATION
s ACCESS TIME:
– 80ns at VCC = 3.0V to 3.6V
– 100ns at VCC = 2.7V to 3.6V
s PIN COMPATIBLE with M27C4002
s LOW POWER CONSUMPTION:
– 15µA max Standby Current
– 15mA max Active Current at 5MHz
s PROGRAMMING TIME 100µs/word
s HIGH RELIABILITY CMOS TECHNOLOGY
– 2,000V ESD Protection
– 200mA Latchup Protection Immunity
s ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code: 0044h
40
1
FDIP40W (F)
40
1
PDIP40 (B)
PLCC44 (K)
TSOP40 (N)
10 x 20 mm
Figure 1. Logic Diagram
DESCRIPTION
The M27W402 is a low voltage 4 Mbit EPROM of-
fered in the two range UV (Ultra Violet Erase) and
OTP (one time programmable). It is ideally suited
for microprocessor systems requiring large data or
program storage and is organised as 262,144 by
16 bits.
The M27W402 operates in the read mode with a
supply voltage as low as 2.7V at –40 to 85°C tem-
perature range. The decrease in operating power
allows either a reduction of the size of the battery
or an increase in the time between battery re-
charges.
The FDIP40W (window ceramic frit-seal package)
has a transparent lids which allow the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M27W402 is offered in PDIP40, PLCC44 and
TSOP40 (10 x 20 mm) packages.
VCC VPP
18
A0-A17
16
Q0-Q15
E M27W402
G
VSS
AI01863
March 2000
1/15
1 page  
M27W402
Table 7. Read Mode DC Characteristics (1)
(TA = –40 to 85°C; VCC = 2.7V to 3.6V; VPP = VCC)
Symbol
Parameter
Test Condition
Min
ILI Input Leakage Current
ILO Output Leakage Current
ICC Supply Current
ICC1 Supply Current (Standby) TTL
ICC2 Supply Current (Standby) CMOS
IPP Program Current
0V ≤ VIN ≤ VCC
0V ≤ VOUT ≤ VCC
E = VIL, G = VIL,
IOUT = 0mA, f = 5MHz,
VCC ≤ 3.6V
E = VIH
E > VCC – 0.2V,
VCC ≤ 3.6V
VPP = VCC
VIL Input Low Voltage
–0.6
VIH (2) Input High Voltage
0.7 VCC
VOL Output Low Voltage
IOL = 2.1mA
VOH Output High Voltage TTL
IOH = –400µA
2.4
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Maximum DC voltage on Output is VCC +0.5V.
Max
±10
±10
15
1
15
10
0.2 VCC
VCC + 0.5
0.4
Unit
µA
µA
mA
mA
µA
µA
V
V
V
V
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, the product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection.
The two line control function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
output capacitive and inductive loading of the de-
vice. The associated transient voltage peaks can
be suppressed by complying with the two line out-
put control and by properly selected decoupling
capacitors. It is recommended that a 0.1µF ceram-
ic capacitor be used on every device between VCC
and VSS. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7µF bulk electrolytic capacitor should be
used between VCC and VSS for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point.The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
5/15
5 Page 
M27W402
Table 13. FDIP40W - 40 pin Ceramic Frit-seal DIP with window, Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max
A 5.72 0.225
A1
0.51 1.40
0.020
0.055
A2
3.91 4.57
0.154
0.180
A3
3.89 4.50
0.153
0.177
B
0.41 0.56
0.016
0.022
B1 1.45
–
– 0.057 –
–
C
0.23 0.30
0.009
0.012
D
51.79
52.60
2.039
2.071
D2 48.26
–
– 1.900 –
–
E 15.24 –
– 0.600 –
–
E1
13.06
13.36
0.514
0.526
e 2.54 –
– 0.100 –
–
eA 14.99
–
– 0.590 –
–
eB
16.18
18.03
0.637
0.710
L
3.18 4.10
0.125
0.161
S
1.52 2.49
0.060
0.098
∅ 7.62
–
– 0.300 –
–
α
4° 11°
4° 11°
N 40
40
Figure 8. FDIP40W - 40 pin Ceramic Frit-seal DIP with window, Package Outline
A2 A3 A
A1 L
B1 B e
D2
S
N
D
∅
E1 E
1
Drawing is not to scale.
α
C
eA
eB
FDIPW-a
11/15
11 Page | ||
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| PDF Descargar | [ Datasheet M27W402-120B6TR.PDF ] | |
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