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PDF DS75365 Data sheet ( Hoja de datos )

Número de pieza DS75365
Descripción Quad TTL-to-MOS Driver
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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No Preview Available ! DS75365 Hoja de datos, Descripción, Manual

June 1992
DS75365 Quad TTL-to-MOS Driver
General Description
The DS75365 is a quad monolithic integrated TTL-to-MOS
driver and interface circuit that accepts standard TTL input
signals and provides high-current and high-voltage output
levels suitable for driving MOS circuits It is used to drive
address control and timing inputs for several types of MOS
RAMs including the 1103
The DS75365 operates from the TTL 5V supply and the
MOS VSS and VBB supplies in many applications This de-
vice has been optimized for operation with VCC2 supply volt-
age from 16V to 20V and with nominal VCC3 supply voltage
from 3V to 4V higher than VCC2 However it is designed so
as to be usable over a much wider range of VCC2 and VCC3
In some applications the VCC3 power supply can be elimi-
nated by connecting the VCC3 to the VCC2 pin
Features
Y Quad positive-logic NAND TTL-to-MOS driver
Y Versatile interface circuit for use between TTL and
high-current high-voltage systems
Y Capable of driving high-capacitance loads
Y Compatible with many popular MOS RAMs
Y Interchangeable with Intel 3207
Y VCC2 supply voltage variable over side range to 24V
maximum
Y VCC3 supply voltage pin available
Y VCC3 pin can be connected to VCC2 pin in some
applications
Y TTL compatible diode-clamped inputs
Y Operates from standard bipolar and MOS supply
voltages
Y Two common enable inputs per gate-pair
Y High-speed switching
Y Transient overdrive minimizes power dissipation
Y Low standby power dissipation
Schematic and Connection Diagrams
Dual-In-Line Package
TL F 7560 – 2
Top View
Positive Logic Y e AE1E2
Order Number DS75365N or DS75365WM
See NS Package Number M16B or N16A
TL F 7560 – 1
C1995 National Semiconductor Corporation TL F 7560
RRD-B30M105 Printed in U S A

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DS75365 pdf
FIGURE 2 Interconnection of DS75365 Devices
with 1103-Type Silicon-Gate MOS RAM
TL F 7560 – 7
Typical Applications
The fast switching speeds of this device may produce unde-
sirable output transient overshoot because of load or wiring
inductance A small series damping resistor may be used to
reduce or eliminate this output transient overshoot The op-
timum value of the damping resistor depends on the specific
load characteristics and switching speed A typical value
would be between 10X and 30X (Figure 3 )
Note RD j 10X to 30X (Optional)
TL F 7560 – 8
FIGURE 3 Use of Damping Resistor to Reduce or
Eliminate Output Transient Overshoot in Certain
DS75365 Applications
Thermal Information
POWER DISSIPATION PRECAUTIONS
Significant power may be dissipated in the DS75365 driver
when charging and discharging high-capacitance loads over
a wide voltage range at high frequencies The total dissipa-
tion curve shows the power dissipated in a typical DS75365
as a function of load capacitance and frequency Average
power dissipation by this driver can be broken into three
components
PT(AV) e PDC(AV) a PC(AV) a PS(AV)
where PDC(AV) is the steady-state power dissipation with the
output high or low PC(AV) is the power level during charging
or discharging of the load capacitance and PS(AV) is the
power dissipation during switching between the low and
high levels None of these include energy transferred to the
load and all are averaged over a full cycle
The power components per driver channel are
PDC(AV)
e
PLtL
a
T
PHtH
PC(AV) j C VC2f
PS(AV)
e
PLHtLH
a
T
PHLtHL
where the times are as defined in Figure 4
PL PH PLH and PHL are the respective instantaneous lev-
els of power dissipation and C is load capacitance
The DS75365 is so designed that PS is a negligible portion
of PT in most applications Except at very high frequencies
tL a tH n tLH a tHL so that PS can be neglected The total
dissipation curve for no load demonstrates this point The
power dissipation contributions from all four channels are
then added together to obtain total device power
The following example illustrates this power calculation
technique Assume all four channels are operating identical-
ly with C e 100 pF f e 2 MHz VCC1 e 5V VCC2 e 20V
VCC3 e 24V and duty cycle e 60% outputs high
(tH T e 0 6) Also assume VOH e 20V VOL e 0 1V PS is
negligible and that the current from VCC2 is negligible when
the output is low
On a per-channel basis using data sheet values
 J  J4 mA
b2 2 mA
PDC(AV) e (5V) 4 a (20V) 4 a (24V)
 J (  J2 2 mA
31 mA
(0 6) a (5V)
a
44
 J  J (0 mA
16 mA
(20V)
a (24V)
(0 4)
44
PDC(AV) e 58 mW per channel
PC(AV) j (100 pF) (19 9V)2 (2 MHz)
PC(AV) j 79 mW per channel
For the total device dissipation of the four channels
PT(AV) j 4 (58 a79)
PT(AV) j 548 mW typical for total package
FIGURE 4 Output Voltage Waveform
5
TL F 7560 – 9

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