|
|
PDF DS4000N Data sheet ( Hoja de datos )
| Número de pieza | DS4000N | |
| Descripción | Digitally Controlled TCXO | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de DS4000N (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
www.maxim-ic.com
GENERAL DESCRIPTION
The DS4000 digitally controlled temperature-compen-
sated crystal oscillator (DC-TCXO) features a digital
temperature sensor, one fixed-frequency temperature-
compensated square-wave output (F1), one
programmable temperature-compensated square-
wave output (F2), and digital communication for
frequency tuning (SDA, SCL).
APPLICATIONS
Reference Oscillators in PLL Circuits
Global Positioning Systems
SATCOM
Telecom
Wireless Base Stations
ORDERING INFORMATION
PART
DS4000
DS4000N
TEMP RANGE
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
24 BGA
24 BGA
Selector Guide appears end of data sheet.
DS4000
Digitally Controlled TCXO
FEATURES
§ Aging ≤1.0ppm (First Year)
§ Frequency Stability ±1.0ppm from -40°C to +85°C
§ Frequency Versus Supply Stability of ±1.0ppm per
Volt
Base Frequency is Digitally Tunable by ±10ppm
One Fixed-Frequency Output and One
(n + 1) or 2(n + 1) Division of the Base
Frequency Output
§ Temperature Measurements from -40C° to +85°C
with 10-Bit/+0.25°C Resolution and ±3°C
Accuracy
§ 2-Wire Serial Interface
PIN CONFIGURATION
TOP VIEW
AB
SCL
6
SDA
5
A0 4
GNDOSC
N.C.
3
2
GND
1
CD
F2
VCC
F1
VOSC
GND
GND
BGA
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
1 of 16
REV: 072403
1 page  
Figure 1. Timing Diagram
DS4000 Digitally Controlled TCXO
PIN DESCRIPTION
PIN
1A, 1B, 1C,
1D, 2C, 2D
2A, 2B
NAME
GND
N.C.
FUNCTION
Ground. DC power is provided to the device on these pins.
No Connection. (Do not connect to ground.)
3A, 3B
GNDOSC Oscillator Ground. DC power is provided to the oscillator on these pins.
3C, 3D
4A, 4B
4C, 4D
5A, 5B
5C, 5D
6A, 6B
6C, 6D
VOSC
A0
F1
SDA
VCC
SCL
F2
Oscillator Power Supply. DC power is provided to the oscillator on these pins.
2-Wire Slave Address Input. This pin is used to configure the slave address.
DC-TCXO Frequency Output
2-Wire Serial-Data Input/Output. SDA is the input/output pin for the 2-wire serial
interface. The SDA pin is open drain and requires an external pullup resistor.
Power Supply. DC power is provided to the device on these pins.
2-Wire Serial-Clock Input. SCL is used to synchronize data movement on the serial
interface. The SCL pin is open drain and requires an external pullup resistor.
DC-TCXO Frequency Output
5 of 16
5 Page 
DS4000 Digitally Controlled TCXO
2-WIRE SERIAL INTERFACE
The DS4000 supports a bidirectional 2-wire serial bus and data transmission protocol. The bus must be controlled
by a master device, which generates the serial clock (SCL), controls the bus access, and generates the START
and STOP conditions. The DS4000 operates as a slave on the 2-wire bus. The DS4000 works in a regular mode
(100kHz clock rate) and a fast mode (400kHz clock rate), which are defined within the bus specifications.
Connections to the bus are made by the open-drain I/O signals SDA and SCL.
The following bus protocol has been defined (Figure 3):
§ Data transfer can be initiated only when the bus is not busy.
§ During data transfer, the data signal must remain stable whenever the clock signal is HIGH. Changes in the
data signal while the clock signal is HIGH are interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus Not Busy: Both data and clock signals remain HIGH.
Start Data Transfer: A change in the state of the data signal, from HIGH to LOW, while the clock line is HIGH,
defines the START condition.
Stop Data Transfer: A change in the state of the data signal, from LOW to HIGH, while the clock line is HIGH,
defines the STOP condition.
Data Valid: The state of the data signal represents valid data when, after a START condition, the data signal is
stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the
LOW period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions is not limited and is determined by the master device. The
information is transferred byte-wise and each receiver acknowledges with a ninth bit.
Acknowledge: Each receiving device, when addressed, is required to generate an acknowledge after reception of
each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit.
A device that acknowledges must pull down the serial data (SDA) signal during the acknowledge clock pulse in
such a way that the SDA signal is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end-of-data to the slave by not
generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must
leave the data signal HIGH to enable the master to generate the STOP condition.
11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet DS4000N.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DS4000 | Digitally Controlled TCXO | Dallas Semiconducotr |
| DS4000N | Digitally Controlled TCXO | Dallas Semiconducotr |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |