|
|
PDF DS3885V Data sheet ( Hoja de datos )
| Número de pieza | DS3885V | |
| Descripción | BTL Arbitration Transceiver | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de DS3885V (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
|
No Preview Available !
January 1994
DS3885 BTL Arbitration Transceiver
General Description
The DS3885 is one in a series of transceivers designed spe-
cifically for the implementation of high performance Future-
busa and proprietary bus interfaces The DS3885 Arbitra-
tion Transceiver is designed to conform to IEEE 1194 1
(Backplane Transceiver Logic BTL) as specified in the
IEEE 896 2 Futurebusa specification The Arbitration
Transceiver incorporates the competition logic internally
which simplifies the implementation of a Futurebusa appli-
cation by minimizing the on board logic required
The DS3885 driver output configuration is an NPN open col-
lector which allows Wired-OR connection on the bus Each
driver output incorporates a Schottky diode in series with its
collector to isolate the transistor output capacitance from
the bus thus reducing the bus loading in the inactive state
The BTL drivers also have high sink current capability to
comply with the bus loading requirements defined within
IEEE 1194 1 BTL specification
Backplane Transceiver Logic (BTL) is a signaling standard
that was invented and first introduced by National Semicon-
(Continued)
Features
Y 9-bit inverting BTL transceiver
Y Meets IEEE 1194 1 standard on Backplane Transceiver
Logic (BTL)
Y Includes on chip competition logic and parity checking
Y Supports live insertion
Y Glitch free power-up down protection
Y Typically less than 5 pF bus-port capacitance
Y Low bus-port voltage swing (typically 1V) at 80 mA
Y Open collector bus-port output allows Wired-OR
connection
Y Exceeds 2 kV ESD testing (Human Body Model)
Y Individual bus-port ground pins minimize ground bounce
Y Controlled rise and fall time to reduce noise coupling to
adjacent lines
Y TTL compatible driver and control inputs
Y Built in bandgap reference with separate QVCC and
QGND pins for precise receiver thresholds
Y Product offered in PLCC and PQFP package styles
Connection Diagrams
TL F 10721 – 2
Order Number DS3885V or DS3885VF
See NS Package Number V44A or VF44B
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 10721
TL F 10721 – 13
RRD-B30M75 Printed in U S A
1 page  
AC Electrical Characteristics TA e 0 C to a70 C VCC e 5V g10% (Note 6) (Continued)
Symbol
Parameter
Conditions Min Typ Max
PARAMETERS NOT TESTED
Coutput
Capacitance at Bn
(Note 7)
5
tNR Noise Rejection
(Note 8)
1
Note 6 All input rise fall times should be 3 ns
Note 7 This parameter is tested using TDR techniques described in 1194 0 BTL Backplane Design Guide
Note 8 This parameter is tested during device characterization The measurement revealed that the part will typically reject 1 ns pulse width
Units
pF
ns
Pin Description
Pin Name
Number of
Pins
Input
Output
Description
ALL1
1 O TTL All asserted (A logic ‘‘1’’ indicates that all the competition bits
are asserted )
ABk7 0l
8 I O BTL Futurebusa Wired-OR competition bits
ABP 1 I O BTL Futurebusa Wired-OR competition parity bit
ABk7 0l and
ABP GND
9
NA Parallel driver grounds reduce ground bounce due to high current
switching of driver outputs (Note 9)
CNk7 0l
8 I O TTL TRI-STATE Module competition bits
CNP
1 I TTL TRI-STATE Module competition parity bit
CMPT
1 I TTL Competition bit (A logic ‘‘0’’ indicates that the module will
compete in the arbitration )
GND
3 NA Ground for switching circuits (Note 9)
CN LE
1 I TTL CNn latch enable (A logic ‘‘0’’ indicates that the CNknl
logic states are latched with corresponding parity bit)
LI 1 NA Power supply for live insertion Boards that require live insertion
should connect LI to the live insertion pin on the connector
(Note 10)
NC 3 NA No connect
PER
1 O TTL ABn odd parity (A logic ‘‘0’’ indicates parity error)
AB RE
1 I TTL Receiver Enable (A logic ‘‘0’’ enables receivers)
QGND
1 NA Ground for receiver input bandgap reference and non-switching
circuits (Note 9)
QVCC
1 NA VCC supply for bandgap reference and non-switching circuits
(Note 2)
VCC
WIN GT
2 NA VCC supply for switching circuits (Note 10)
1 O TTL Win signal (active low) During competition WIN GT
indicates that the module has won the competition For a module
not participating in the competition WIN GT indicates that the
module has a number which is greater than winner’s number
Note 9 The multiplicity of parallel ground paths reduces the effective inductance of bonding wires and leads which then reduces the noise caused by transients
on the ground path The various ground pins can be tied together provided that the external ground has low inductance (i e ground plane with power pins and
many signal pins connected to the backplane ground) If the external ground floats considerably during transients precautionary steps should be taken to prevent
QGND from moving with reference to the backplane ground The receiver threshold should have the same ground reference as the signal coming from the
backplane A voltage offset between their grounds will degrade the noise margin
Note 10 The same considerations for ground are used for VCC in reducing lead inductance (See Note 9) QVCC and VCC should be tied together externally If live
insertion is not supported the LI pin can be tied together with QVCC and VCC
5
5 Page 
Physical Dimensions inches (millimeters)
44-Lead Plastic Chip Carrier
Order Number DS3885V
NS Package Number V44A
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet DS3885V.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DS3885 | BTL Arbitration Transceiver | National Semiconductor |
| DS3885 | DS3885 BTL Arbitration Transceiver MIL-STD-883 (Rev. A) |  Texas Instruments |
| DS3885V | BTL Arbitration Transceiver | National Semiconductor |
| DS3885VF | BTL Arbitration Transceiver | National Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |