|
|
PDF DS26556 Data sheet ( Hoja de datos )
| Número de pieza | DS26556 | |
| Descripción | 4-Port Cell/Packet Over T1/E1/J1 Transceiver | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de DS26556 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
www.maxim-ic.com
DS26556
4-Port Cell/Packet Over T1/E1/J1
Transceiver
GENERAL DESCRIPTION
The DS26556 is a quad, software-selectable T1,
E1, or J1 transceiver with a cell/packet/TDM
interface. It is composed of four framer/formatters
+ LIUs, and a UTOPIA (cell), POS-PHY™
(packet), and TDM backplane interface. Each
framer has an HDLC controller that can be
mapped to any DS0 or FDL (T1)/Sa (E1) bit. The
DS26556 also includes full-featured BERT
devices per port, and an internal clock adapter
useful for creating synchronous, high-frequency
backplane timing. The DS26556 is controlled
through an 8-bit parallel port that can be
configured for nonmultiplexed Intel or Motorola
operation.
APPLICATIONS
Routers
Add-Drop Multiplexers
DSLAMs
PBXs
Switches
Central Office
Equipment
IMA
ATM
WAN Interface
Customer-Premise
Equipment
POS-PHY and POS-PHY Level 3 are trademarks of PMC-Sierra, Inc.
FEATURES
§ Four Independent, Full-Featured T1/E1/J1
Transceivers
§ UTOPIA 2 and 3 Cell Interface
§ POS-PHY 2 and 3 Packet Interface
§ TDM Backplane Supports TDM Bus Rates
from 1.544MHz to 16.384MHz
§ Alarm Detection and Insertion
§ Full-Featured BERT for Each Port
§ AMI, B8ZS, HDB3, NRZ Line Coding
§ Transmit Synchronizer
§ BOC Message Controller (T1)
§ One HDLC Controller per Framer
§ Performance Monitor Counters
§ RAI-CI and AIS-CI Support
§ Internal Clock Generator (CLAD) Supplies
16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz
§ JTAG Test Port
§ Single 3.3V Supply with 5V Tolerant Inputs
§ 17mm x 17mm, 256-Pin BGA (1.00mm
Pitch)
ORDERING INFORMATION
PART
TEMP RANGE
PIN-
PACKAGE
DS26556
0°C to +70°C 256 BGA
DS26556N -40°C to +85°C 256 BGA
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
1 REV: 012105
1 page  
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.7 E1 TRANSMIT FRAMER................................................................................................................................293
11.7.1 Transmit Master Mode Register........................................................................................................................296
11.7.2 Interrupt Information Registers .........................................................................................................................297
11.7.3 E1 Transmit Control Registers..........................................................................................................................297
11.7.4 E1 Transmit Status and Information .................................................................................................................300
11.7.5 Per-Channel Loopback .....................................................................................................................................302
11.7.6 E1 Transmit DS0 Monitoring Function ..............................................................................................................303
11.7.7 E1 Transmit Signaling Operation ......................................................................................................................304
11.7.8 E1 Transmit Per-Channel Idle Code Insertion ..................................................................................................308
11.7.9 E1 Transmit Channel Mark Registers ...............................................................................................................309
11.7.10 Fractional E1 Support (Gapped Clock Mode) ...................................................................................................309
11.7.11 Additional (Sa) and International (Si) Bit Operation (E1 Mode) ........................................................................310
11.7.12 E1 Transmit HDLC Controller ...........................................................................................................................317
11.7.13 Interfacing the E1 Transmitter to the BERT ......................................................................................................323
11.7.14 E1 Transmit Synchronizer.................................................................................................................................325
12 LINE INTERFACE UNIT (LIU)
327
12.1 LIU REGISTERS .........................................................................................................................................328
13 BIT ERROR RATE TESTER (BERT)
335
13.1 BERT REGISTER BIT DESCRIPTIONS ..........................................................................................................336
14 JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
342
14.1 TAP CONTROLLER STATE MACHINE ...........................................................................................................343
14.2 INSTRUCTION REGISTER .............................................................................................................................345
14.3 TEST REGISTERS .......................................................................................................................................346
15 PIN ASSIGNMENT
347
16 PACKAGE MECHANICAL INFORMATION
348
17 PACKAGE THERMAL INFORMATION
349
18 ABSOLUTE MAXIMUM RATINGS
350
19 AC TIMING
351
19.1
19.2
19.3
19.4
19.5
19.6
TRANSMIT TDM PORT AC CHARACTERISTICS .............................................................................................353
RECEIVE TDM PORT AC CHARACTERISTICS ...............................................................................................354
HIGH SPEED PORT AC CHARACTERISTICS ..................................................................................................355
SYSTEM INTERFACE AC CHARACTERISTICS.................................................................................................356
MICROPROCESSOR BUS AC CHARACTERISTICS ..........................................................................................358
JTAG INTERFACE TIMING ...........................................................................................................................361
20 REVISION CHANGE HISTORY
362
5 of 362
5 Page 
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
§ Transmitter power-down
§ Transmitter 50mA short-circuit limiter with current-limit-exceeded indication
§ Transmit open-circuit-detected indication
2.1.3 Clock Synthesizer
§ Output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, and 16.384MHz
§ Derived from recovered receive clock
2.1.4 HDLC Controllers
§ HDLC Engine (One per Framer):
§ Independent 64-byte Rx and Tx Buffers with Interrupt Support
§ Access FDL, Sa, or Single DS0 Channel
§ Compatible with Polled or Interrupt Driven Environments
2.1.5 Test and Diagnostics
§ Full-Featured BERTs
· Programmable PRBS pattern – The Pseudo Random Bit Sequence (PRBS) polynomial (xn + xy + 1) and
seed are programmable (length n = 1 to 32, tap y = 1 to n - 1, and seed = 0 to 2n - 1).
· Programmable repetitive pattern – The repetitive pattern length and pattern are programmable (the length n
= 1 – 32 and pattern = 0 – 2n - 1).
· 24-bit error count and 32-bit bit count registers
· Programmable bit error insertion – Errors can be inserted individually, on a pin transition, or at a specific
rate. The rate 1/10n is programmable (n = 1 to 7).
· Pattern synchronization at a 10-3 BER – Pattern synchronization will be achieved even in the presence of a
random Bit Error Rate (BER) of 10-3.
§ BPV Insertion
§ F-Bit Corruption for Line Testing
§ Loopbacks
Remote
Local
Per-Channel
§ IEEE 1149.1 Support
2.2 Cell/Packet Interface
2.2.1 General
· Programmable system interface type – When performing cell mapping/demapping, the system interface can
be programmed as a UTOPIA Level 2 Bus or a UTOPIA Level 3 Bus or a POS-PHY Level 2 or Level 3 Bus.
When performing packet mapping/demapping, the system interface can be programmed as a POS-PHY Level
2 Bus or a POS-PHY Level 3 Bus.
· Selectable system interface bus width – The data bus can be a 16-bit or 8-bit bus.
· Supports clock speeds up to 52 MHz.
· Supports multiple ports on the system interface – Each line has its own port address for access via the
system interface.
· Programmable system interface port address – The address assigned to each system interface port is
programmable to allow multiple devices to operate on the same bus.
· Supports per port system loopback – Each port has can be placed in system loopback which causes
cells/packets from the transmit FIFO to looped back to the receive FIFO.
· System interface bit/byte reordering – In 16-bit mode the order of the bytes as transferred across the system
interface is programmable, i.e., the first byte received/transmitted can be transferred in ([15:8]) or [7:0]. The
order of the bits as transferred across the system interface is programmable on a per port basis, i.e., the first bit
received/transmitted can be transferred in bit position 7 (15 and 7) or bit position 0 (8 and 0).
11 of 362
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DS26556.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DS26556 | 4-Port Cell/Packet Over T1/E1/J1 Transceiver | Maxim Integrated Products |
| DS26556N | 4-Port Cell/Packet Over T1/E1/J1 Transceiver | Maxim Integrated Products |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |