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PDF DS21Q42 Data sheet ( Hoja de datos )
| Número de pieza | DS21Q42 | |
| Descripción | Enhanced QUAD T1 FRAMER | |
| Fabricantes | Dallas Semiconducotr | |
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DS21Q42
Enhanced QUAD T1 FRAMER
www.dalsemi.com
FEATURES
Four T1 DS1/ISDN–PRI/J1 framing
transceivers
All four framers are fully independent
Each of the four framers contain dual two–
frame elastic store slip buffers that can connect
to asynchronous backplanes up to 8.192 MHz
8–bit parallel control port that can be used
directly on either multiplexed or non–
multiplexed buses (Intel or Motorola)
Programmable output clocks for Fractional T1
Fully independent transmit and receive
functionality
Integral HDLC controller with 64-byte buffers
configurable for FDL or DS0 operation
Generates and detects in–band loop codes from
1 to 8 bits in length including CSU loop codes
Pin compatible with DS21Q44 E1 Enhanced
Quad E1 Framer
3.3V supply with 5V tolerant I/O; low power
CMOS
Available in 128–pin TQFP package
IEEE 1149.1 support
FUNCTIONAL DIAGRAM
Receive
Framer
Elastic
Store
Transmit
Formatter
FRAMER #0
FRAMER #1
FRAMER #2
FRAMER #3
Elastic
Store
Control Port
ACTUAL SIZE
QUAD
T1
FRAMER
ORDERING INFORMATION
DS21Q42T (00 C to 700 C)
DS21Q42TN (-400 C to +850 C)
DESCRIPTION
The DS21Q42 is an enhanced version of the DS21Q41B Quad T1 Framer. The DS21Q42 contains four
framers that are configured and read through a common microprocessor compatible parallel port. Each
framer consists of a receive framer, receive elastic store, transmit formatter and transmit elastic store. All
four framers in the DS21Q42 are totally independent, they do not share a common framing synchronizer.
Also the transmit and receive sides of each framer are totally independent. The dual two-frame elastic
stores contained in each of the four framers can be independently enabled and disabled as required. The
device fully meets all of the latest T1 specifications including ANSI T1.403–1995, ANSI T1.231–1993,
AT&T TR 62411 (12–90), AT&T TR54016, and ITU G.704 and G.706.
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031500
1 page  
TABLE OF CONTENTS
DS21Q42
1. INTRODUCTION .............................................................................................................................. 2
2. DS21Q42 PIN DESCRIPTION ......................................................................................................... 8
3. DS21Q42 PIN FUNCTION DESCRIPTION ................................................................................ 15
4. DS21Q42 REGISTER MAP............................................................................................................. 22
5. PARALLEL PORT........................................................................................................................... 26
6. CONTROL, ID AND TEST REGISTERS ..................................................................................... 26
7. STATUS AND INFORMATION REGISTERS............................................................................. 37
8. ERROR COUNT REGISTERS....................................................................................................... 45
9. DS0 MONITORING FUNCTION................................................................................................... 48
10. SIGNALING OPERATION ............................................................................................................ 50
10.1. PROCESSOR BASED SIGNALING ................................................................................... 50
10.2. HARDWARE BASED SIGNALING ................................................................................... 52
11. PER–CHANNEL CODE (IDLE) GENERATION AND LOOPBACK....................................... 53
11.1. TRANSMIT SIDE CODE GENERATION ............................................................................ 53
11.1.1. Simple Idle Code Insertion and Per–Channel Loopback ................................................. 54
11.1.2. Per–Channel Code Insertion ........................................................................................... .55
11.2. RECEIVE SIDE CODE GENERATION ................................................................................ 55
11.2.1. Simple Code Insertion .................................................................................................... 55
11.2.2. Per–Channel Code Insertion ............................................................................................. 56
12. CLOCK BLOCKING REGISTERS .............................................................................................. 57
13. ELASTIC STORES OPERATION .............................................................................................. 58
13.1. RECEIVE SIDE ....................................................................................................................... 58
13.2. TRANSMIT SIDE ................................................................................................................... 58
13.3. MINIMUM DELAY SYNCHRONOUS RSYSCLK/TSYSCLK MODE .............................. 59
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5 Page 
DS21Q42
PIN SYMBOL TYPE DESCRIPTION
122
D5 or AD5
I/O Data Bus Bit or Address/Data Bit 5
123
D6 or AD6
I/O Data Bus Bit or Address/Data Bit 6
124
D7 or AD7
I/O Data Bus Bit or Address/Data Bit 7; MSB
125 TSYSCLK0 I Transmit System Clock for Elastic Store in Framer 0
126 TSER0 I Transmit Serial Data for Framer 0
127 TSSYNC0 I Transmit Sync for Elastic Store in Framer 0
128
TSIG0
I Transmit Signaling Input for Framer 0
[TCHCLK0] [O] [Transmit Channel Clock from Framer 0]
Note:
1. Brackets [ ] indicate pin function when the DS21Q42 is configured for emulation of the DS21Q41B,
(FMS = 1).
11 of 119
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DS21Q42.PDF ] | |
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