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PDF DS2187 Data sheet ( Hoja de datos )
| Número de pieza | DS2187 | |
| Descripción | Receive Line Interface | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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FEATURES
Line interface for T1 (1.544 MHz) and CEPT
(2.048 MHz) primary rate networks
Extracts clock and data from twisted pair or
coax
Meets requirements of PUB 43801, TR
62411, and applicable CCITT G.823
Precision on-chip PLL eliminates external
crystal or LC tank - no tuning required
Decodes AMI, B8ZS, and HDB3 coded
signals
Designed for short loop applications such as
terminal equipment to DSX-1
Reports alarm and error events
Compatible with the DS2180A T1/ISDN
Primary Rate and DS2181A CEPT
Transceivers, as well as DS2141A T1 and
DS2143 E1 Controllers
Companion to the DS2186 T1/CEPT
Transmit Line Interface and DS2188
T1/CEPT Jitter Attenuator
Single 5V supply; low-power CMOS
technology
DS2187
Receive Line Interface
PIN ASSIGNMENT
AVDD 1
20 DVDD
RAIS 2
19 RCL
ZCSEN 3
18 AIS
NC 4
17 BPV
LCAP 5
16 NC
RCLKSEL 6
15 NC
RTIP 7
14 RPOS
RRING 8
13 RNEG
LOCK 9
12 RCLK
AVSS 10
11 DVSS
20-Pin SOIC (300-mil)
AVDD 1
18 DVDD
RAIS 2
17 RCL
ZCSEN 3
16 AIS
LCAP 4
15 BPV
RCLKSEL 5
14 NC
RTIP 6
13 RPOS
RRING 7
12 RNEG
LOCK 8
11 RCLK
AVSS 9
10 DVSS
18-Pin DIP (300-mil)
DESCRIPTION
The DS2187 T1/CEPT Receive Line Interface chip interfaces user equipment to North American (T1
1.544 MHz) and European (CEPT 2.048 MHz) primary rate communication networks. The device
extracts clock and data from twisted pair or coax transmission media and eliminates expensive discrete
components and/or manual tuning required in existing T1 and CEPT line termination electronics.
Application areas include DACS, CSU, CPE, channel banks, and PABX-to-computer interfaces such as
DMI and CPI.
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DS2187
0 CODE SUPPRESSION
The device will decode incoming B8ZS (RCLKSEL=0) or HDB3 (RCLKSEL=1) code words and replace
them with an all-0 code when ZCSEN=1. When ZCSEN=0, code words will pass through the device
without being altered. This feature can be disabled when the DS2187 is used with transceiver devices
such as the DS2180A DS2181A, DS2141A, or DS2143.
ALARM DETECTION
The extracted data is monitored for network alarm and error conditions. RCL is set when 192 consecutive
0s occur; it is cleared on the next one occurrence. AIS is set when less than three 0s have appeared at
RPOS and RNEG during the last two periods of the RAIS signal; once set, AIS will remain high for the
next two periods of RAIS . AIS will return low when more than two 0s appear. BPV reports bipolar
violations as they occur at RPOS and RNEG; B8ZS code words will not be flagged by BPV when
ZCSEN=1.
BYPASSING AND
LAYOUT CONSIDERATIONS
The DS2187 contains both precision analog and high-speed digital circuitry on the same chip. The power
supplies of these circuits (AVDD, AVSS, DVDD and DVSS) should be connected to system analog and
digital supplies. If separate system supplies do not exist, the appropriate supply pins can be tied together.
Tying the analog and digital supplies together on the DS2187 will not degrade its performance, provided
the power supply is sufficiently decoupled.
To assure optimum performance, the length of LCAP, RTIP and RRING printed circuit board traces
should be minimized and isolated from neighboring interconnect.
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5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet DS2187.PDF ] | |
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