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PDF DS2181A Data sheet ( Hoja de datos )
| Número de pieza | DS2181A | |
| Descripción | CEPT Primary Rate Transceiver | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DS2181A (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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DS2181A
CEPT Primary Rate Transceiver
www.dalsemi.com
FEATURES
Single chip primary rate transceiver meets
CCITT standards G.704, G.706 and G.732
Supports new CRC4-based framing
standards and CAS and CCS signaling
standards
Simple serial interface used for device
configuration and control in processor mode
Hardware mode requires no host processor;
intended for stand-alone applications
Comprehensive, on-chip alarm generation,
alarm detection, and error logging logic
Shares footprint with DS2180A T1
Transceiver
Comparison to DS2175 T1/CEPT Elastic
Store, DS2186 Transmit Line Interface,
DS2187 Receive Line Interface, and DS2188
Jitter Attenuator
PIN ASSIGNMENT
TMSYNC
TFSYNC
TCLK
TCHCLK
TSER
TMO
TXD
TSTS
TSD
TIND
TAF
TPOS
TNEG
INT
SDI
SDO
CS
SCLK
SPS
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VDD
39 RLOS
38 RFER
37 RBV
36 RCL
35 RNEG
34 RPOS
33 RST
32 TEST
31 RCSYNC
30 RSTS
29 RSD
28 RMSYNC
27 RFSYNC
26 RSER
25 RCHCLK
24 RCLK
23 RAF
22 RDMA
21 RRA
40-Pin DIP (600-mil)
5V supply; low-power CMOS technology
TSER
TMO
TXD
TSTS
TSD
TIND
TAF
TPOS
TNEG
INT
SDI
7
8
9
10
11
12
13
14
15
16
17
39 RNEG
38 RPOS
37 RST
36 TEST
44-PIN PLCC
35
34
RCSYNC
RSTS
33 RSD
32 RMSYNC
31 RFSYNC
30 RSER
29 RCHCLK
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DS2181A
PORT PIN DESCRIPTION (40-PIN DIP ONLY) Table 3
PIN SYMBOL TYPE
DESCRIPTION
14 INT
O Receive Alarm Interrupt. Flags host controller during alarm
conditions. Active low; open drain output.
15 SDI
I Serial Data In. Data for on-chip control registers; sampled on rising
edge of SCLK.
16 SDO
O Serial Data Out. Control and status data from on-chip registers.
Updated on falling edge of SCLK; tri-stated during port write or when
CS is high.
17 CS
I Chip Select. Must be low to write or read the serial port.
18 SCLK
I Serial Data Clock. Used to write or read the serial port registers.
19 SPS
I Serial Port Select. Tie to VDD to select the serial port. Tie to VSS to
select the hardware mode.
POWER AND TEST PIN DESCRIPTION (40-PIN DIP ONLY) Table 4
PIN SYMBOL TYPE
DESCRIPTION
20 VSS
32 TEST
- Signal Ground. 0.0 volts.
I Test Mode. Tie to VSS to select the old DS2181 sync algorithm and to
tri–state the synchronizer status pins on the DS2181AQ. Tie to VDD
to select the new DS2181A sync algorithm and activate the
synchronizer status pins on the DS2181AQ.
40 VDD
- Positive Supply. 5.0 volts.
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5 Page 
DS2181A
CCS SIGNALLING
CCS (selected when TCR.5 = 1 and/or when RCR.1 = 1) utilizes all bit positions of timeslot 16 in every
frame for message-oriented signaling data transmission. In CCS mode one can use either timeslot 16 or
any one of the other 30 data channels for message-oriented signaling. The CCS mode has no multiframe
structure and the insertion of CAS multiframe alignment, distant multiframe alarm and/or extra bits into
timeslot 16 is disabled. TSER is the source of timeslot 16 data.
CRC4 CODING
The need for enhanced error monitoring capability and additional protection against emulators of the
frame alignment word has led to the development of a cyclic redundancy check (CRC) procedure. When
enabled via CCR.2 and/or CCR.3, CRC4 coding replaces the international bit positions in frames 0
through 12 and 14 with a CRC4 multiframe alignment pattern and associated checksum words. The
CRC4 multiframe must begin with a frame containing the frame alignment signal (CCR.6 = 0). A rising
edge at TMSYNC establishes the CRC4 multiframe alignment (TMSYNC will also establish outgoing
CAS multiframe alignment if enabled via TCR.5).
Incoming CRC4 multiframe alignment is indicated by RCSYNC. Detected CRC4 checksum errors are re-
ported at output RFER and logged in the CECR.
RECEIVE SYNCHRONIZER
The fixed characteristics of the receive synchronizer may be modified by use of programmable
characteristics resident in the RCR and CCR. Sync criteria must be met before synchronization is
declared. Resync criteria establish error occurrences which will cause an auto-resync event when enabled
(RCR.1 = 0).
The receive synchronizer searches for the frame alignment pattern first. Once identified, the output timing
set associated with the framing pattern (all outputs except RCSYNC and RMSYNC) is updated to that
new alignment. If enabled, the synchronizer then begins CAS and/or CRC4 multiframe search; outputs
RMSYNC and/or RCSYNC are then updated. Output RLOS is held high during the entire resync process,
then transitions low after the last output timing update indicating resync is complete. For more details
about the receive synchronizer, see the separate DS2181A CEPT Transceiver Application Note.
FIXED FRAME SYNC CRITERIA
Valid frame sync is assumed when the correct frame alignment signal is present in frame N and frame N
+ 2 and not present in frame N + 1 (bit 2 of timeslot 0 of Frame N + 1 is also checked for 1). CAS and/or
CRC4 multiframe alignment search is initiated when the frame search is complete if enabled via RCR.5
and/or CCR.2.
FIXED CAS MULTIFRAME SYNC CRITERIA
CAS multiframe sync is declared when the multiframe alignment pattern is properly detected and timeslot
16 of the previous frame contains code other than zeros. If no valid pattern can be found in 12 to 14
milliseconds (no time-out period exists if CCR.1=1 or TEST=1), frame search is restarted.
FIXED CRC4 MULTIFRAME SYNC CRITERIA
CRC4 multiframe sync is declared if at least two valid CRC4 multiframe alignment signals are found
within 12 to 14 milliseconds (8 ms if CCR.1=1 or TEST=1) after frame alignment is completed. If not
found within 12 to 14 milliseconds (8 ms if CCR.1=1 or TEST=1), frame search is restarted. The search
for the multiframe alignment signal is performed in timeslot 0 of frames not containing the frame
alignment signal.
11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DS2181A.PDF ] | |
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