PDF DS2141A Data sheet ( Hoja de datos )

Número de pieza	DS2141A
Descripción	T1 Controller
Fabricantes	Dallas Semiconducotr
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No Preview Available ! www.dalsemi.com FEATURES DS1/ISDN-PRI framing transceiver Frames to D4, ESF, and SLC-96 formats Parallel control port Onboard, dual two-frame elastic store slip buffers Extracts and inserts robbed-bit signaling Programmable output clocks Onboard FDL support circuitry 5V supply; low-power CMOS Available in 40-pin DIP and 44-pin PLCC (DS2141Q) Compatible with DS2186 Transmit Line Interface, DS2187 Receive Line Interface, DS2188 Jitter Attenuator, DS2290 T1 Isolation Stik, and DS2291 T1 Long Loop Stik DS2141A T1 Controller PIN ASSIGNMENT TCLK TSER TCHCLK TPOS TNEG AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 BTS RD(DS) CS ALE(AS) WR(R/W) RLINK VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 VDD 39 TSYNC 38 TLINK 37 TLCLK 36 INT1 35 INT2 34 RLOS/LOTC 33 TCHBLK 32 RCHBLK 31 LI CS 30 LI CLK 29 LI SDI 28 SYSCLK 27 RNEG 26 RPOS 25 RSYNC 24 RSER 23 RCHCLK 22 RCLK 21 RLCLK 40-Pin DIP (600-mil) AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 BTS RD(DS) NC 6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 44-PIN PLCC 34 13 33 14 32 15 31 16 30 17 29 18 19 20 21 22 23 24 25 26 27 28 RLOS/LOTC TCHBLK RCHBLK LI_CS LI_CLK LI_SDI NC NC SYSCLK RNEG RPOS DESCRIPTION The DS2141A is a comprehensive, software-driven T1 framer. It is meant to act as a slave or coprocessor to a microcontroller or microprocessor. Quick access via the parallel control port allows a single micro to handle many T1 lines. The DS2141A is very flexible and can be configured into numerous orientations via software. The software orientation of the device allows the user to modify their design to conform to future T1 specification changes. The controller contains a set of 62 8-bit internal registers which the user can access. These internal registers are used to configure the device and obtain information from the T1 1 of 39 112099 1 page DS2141A PIN SYMBOL TYPE DESCRIPTION 38 TLINK I Transmit Link Data. If enabled via TCR1.2, this pin will be sampled during the F-bit time on the falling edge of TCLK for data insertion into either the FDL stream (ESF) or the Fs-bit position (D4) or the Z-bit position (ZBTSI). See Section 13 for timing details. 39 TSYNC I/O Transmit Sync. A pulse at this pin will establish either frame or multiframe boundaries for the DS2141A. Via TCR2.2, the DS2141A can be programmed to output either a frame or multiframe pulse at this pin. If this pin is set to output pulses at frame boundaries, it can also be set via TCR2.4 to output double-wide pulses at signaling frames. See Section 13 for timing details. 40 VDD - Positive Supply. 5.0 volts. DS2141A REGISTER MAP ADDRESS R/W REGISTER NAME 20 R/W Status Register 1 21 R/W Status Register 2 22 R/W Receive Information Register 23 R Bipolar Violation/ESF Error Event Count Register 1 24 R Bipolar Violation/ESF Error Event Count Register 2 25 R CRC6 Count Register 1 26 R CRC6 Count Register 2 27 R Frame Error Count Register 28 R Receive FDL Register 29 R/W Receive FDL Match Register 1 2A R/W Receive FDL Match Register 2 2B R/W Receive Control Register 1 2C R/W Receive Control Register 2 2D R/W Receive Mark Register 1 2E R/W Receive Mark Register 2 2F R/W Receive Mark Register 3 30 Not Assigned 31 Not Assigned 32 R/W Transmit Channel Blocking Register 1 33 R/W Transmit Channel Blocking Register 2 ADDRESS 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 60 61 62 63 64 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R REGISTER NAME Transmit Channel Blocking Register 3 Transmit Control Register 1 Transmit Control Register 2 Common Control Register 1 Common Control Register 2 Transmit Transparency Register 1 Transmit Transparency Register 2 Transmit Transparency Register 3 Transmit Idle Register 1 Transmit Idle Register 2 Transmit Idle Register 3 Transmit Idle Definition Register Receive Signaling Register 1 Receive Signaling Register 2 Receive Signaling Register 3 Receive Signaling Register 4 Receive Signaling Register 5 5 of 39 5 Page DS2141A CCR1: COMMON CONTROL REGISTER 1 (37h) (MSB) (LSB) TESE P34F RSAO - SCLKM RESE PLB LLB SYMBOL POSITION NAME AND DESCRIPTION TESE CCR1.7 Transmit Elastic Store Enable. 0=elastic store is bypassed. 1=elastic store is enabled. P34F CCR1.6 Function of Pin 34. 0=Receive Loss of Sync (RLOS). 1=Loss of Transmit Clock (LOTC). RSAO CCR1.5 Receive Signaling All 1's. 0=allow robbed signaling bits to appear at RSER. 1=force all robbed signaling bits at RSER to 1. - CCR1.4 Not Assigned. Should be set to 0 when written to. SCLKM CCR1.3 SYSCLK Mode Select. 0=if SYSCLK is 1.544 MHz. 1=if SYSCLK is 2.048 MHz. RESE CCR1.2 Receive Elastic Store Enable. 0=elastic store is bypassed. 1=elastic store is enabled. PLB CCR1.1 Payload Loopback. 0=loopback disabled. 1=loopback enabled. LLB CCR1.0 Local Loopback. 0=loopback disabled. 1=loopback enabled. PAYLOAD LOOPBACK When CCR1.1 is set to a 1, the DS2141A will be forced into Payload LoopBack (PLB). Normally, this loopback is only enabled when ESF framing is being performed. In a PLB situation, the DS2141A will loop the 192 bits of payload data (with BPVs corrected) from the receive section back to the transmit section. The FPS framing pattern, CRC6 calculation, and the FDL bits are not looped back, they are reinserted by the DS2141A. When PLB is enabled, the following will occur: 1. Data will be transmitted from the TPOS and TNEG pins synchronous with RCLK instead of TCLK. 2. All of the receive side signals will continue to operate normally. 3. The TCHCLK and TCHBLK signals are forced low. 4. Data at the TSER pin is ignored. 5. The TLCLK signal will become synchronous with RCLK instead of TCLK. 11 of 39 11 Page

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