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EN29F040-70PI fiches techniques PDF

ETC - 4 Megabit (512K x 8-bit) Flash Memory

Numéro de référence EN29F040-70PI
Description 4 Megabit (512K x 8-bit) Flash Memory
Fabricant ETC 
Logo ETC 





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EN29F040-70PI fiche technique
EN29F040
4 Megabit (512K x 8-bit) Flash Memory
EN29F040
FEATURES
5.0V operation for read/write/erase
operations
Fast Read Access Time
- 45ns, 55ns, 70ns, and 90ns
Sector Architecture:
- 8 uniform sectors of 64Kbytes each
- Supports full chip erase
- Individual sector erase supported
- Sector protection:
Hardware locking of sectors to prevent
program or erase operations within
individual sectors
High performance program/erase speed
- Byte program time: 10µs typical
- Sector erase time: 500ms typical
- Chip erase time: 3.5s typical
Low Standby Current
- 1µA CMOS standby current-typical
- 1mA TTL standby current
Low Power Active Current
- 30mA active read current
- 30mA program/erase current
JEDEC Standard program and erase
commands
JEDEC standard DATA polling and toggle
bits feature
Single Sector and Chip Erase
Sector Unprotect Mode
Embedded Erase and Program Algorithms
Erase Suspend / Resume modes:
Read and program another Sector during
Erase Suspend Mode
0.35 µm double-metal double-poly
triple-well CMOS Flash Technology
Low Vcc write inhibit < 3.2V
100K endurance cycle
Package Options
- 32-pin PDIP
- 32-pin PLCC
- 32-pin TSOP (Type 1)
Commercial and Industrial Temperature
Ranges
GENERAL DESCRIPTION
The EN29F040 is a 4-Megabit, electrically erasable, read/write non-volatile flash memory. Organized
into 512K words with 8 bits per word, the 4M of memory is arranged in eight uniform sectors of
64Kbytes each. Any byte can be programmed typically in 10µs. The EN29F040 features 5.0V
voltage read and write operation, with access times as fast as 45ns to eliminate the need for WAIT
states in high-performance microprocessor systems.
The EN29F040 has separate Output Enable ( OE ), Chip Enable ( CE ), and Write Enable ( W E )
controls, which eliminate bus contention issues. This device is designed to allow either single (or
multiple) Sector or full chip erase operation, where each Sector can be individually protected against
program/erase operations or temporarily unprotected to erase or program. The device can sustain a
minimum of 100K program/erase cycles on each Sector.
4800 Great America Parkway, Suite 202
1
Santa Clara, CA 95054
Rev. D, Issue Date: 2001/07/05
Tel: 408-235-8680
Fax: 408-235-8685

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