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PDF 100398QI Data sheet ( Hoja de datos )
| Número de pieza | 100398QI | |
| Descripción | Quad Differential ECL/TTL Translating Transceiver with Latch | |
| Fabricantes | Fairchild Semiconductor | |
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Hay una vista previa y un enlace de descarga de 100398QI (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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February 1992
Revised August 2000
100398
Quad Differential ECL/TTL Translating Transceiver
with Latch
General Description
The 100398 is a quad latched transceiver designed to con-
vert TTL logic levels to differential F100K ECL logic levels
and vice versa. This device was designed with the capabil-
ity of driving a differential 25Ω ECL load with cutoff capabil-
ity, and will sink a 64 mA TTL load. The 100398 is ideal for
mixed technology applications utilizing either an ECL or
TTL backplane.
The direction of translation is set by the direction control
pin (DIR). The DIR pin on the 100398 accepts TTL logic
levels. A TTL LOW on DIR sets up the ECL pins as inputs
and TTL pins as outputs. A TTL HIGH on DIR sets up the
TTL pins as inputs and ECL pins as outputs.
A LOW on the output enable input pin (OE) holds the ECL
output in a cut-off state and the TTL outputs at a high
impedance level. A HIGH on the latch enable input (LE)
latches the data at both inputs even though only one output
is enabled at the time. A LOW on LE makes the latch trans-
parent.
The cut-off state is designed to be more negative than a
normal ECL LOW level. This allows the output emitter-fol-
lowers to turn off when the termination supply is −2.0V, pre-
senting a high impedance to the data bus. This high
impedance reduces termination power and prevents loss of
low state noise margin when several loads share the bus.
The 100398 is designed with FAST TTL output buffers,
featuring optimal DC drive and capable of quickly charging
and discharging highly capacitive loads. All Inputs have
50 kΩ pull-down resistors.
Features
s Differential ECL input/output structure
s 64 mA FAST TTL outputs
s 25Ω differential ECL outputs with cut-off
s Bi-directional translation
s 2000V ESD protection
s Latched outputs
s 3-STATE outputs
s Voltage compensated operating range = −4.2V to −5.7V
Ordering Code:
Order Number Package Number
Package Description
100398PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100398QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100398QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
FAST is a registered trademark of Fairchild Semiconductor.
© 2000 Fairchild Semiconductor Corporation DS010970
www.fairchildsemi.com
1 page  
Commercial Version (Continued)
ECL-to-TTL DC Electrical Characteristics (Note 10)
VEE = −4.2V to −5.7V, GND = 0V, TC = 0°C to +85°C, CL = 50 pF, VTTL = +4.5V to +5.5V
Symbol
Parameter
Min Typ Max
Units
Conditions
VOH
VOL
VIH
VIL
VDIFF
VCM
IIH
IIL
IOZHT
IOZLT
IOS
ICEX
IZZ
ITTL
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
2.7
2.4
−1165
3.1
2.9
0.3
0.5
−870
V IOH = −3 mA, VTTL = 4.75V
V IOH = −3 mA, VTTL = 4.50V
V IOL = 24 mA, VTTL = 4.50V
mV Guaranteed HIGH Signal for All Inputs
Input LOW Voltage
−1830
−1475
mV Guaranteed LOW Signal for All Inputs
Input Voltage Differential
150
mV Required for Full Output Swing
Common Mode Voltage
GNDECL − 2.0
GNDECL − 0.5
V
Input HIGH Current
Input LOW Current
3-STATE Current Output High
3-STATE Current Output Low
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
VTTL Supply Current
0.50
−650
−100
30
70
−225
50
500
39
27
µA VIN = VIH (Max)
µA VIN = VIL (Min)
µA VOUT = +2.7V
µA VOUT = +0.5V
mA VOUT = 0.0V, VTTL = +5.5V
µA VOUT = 5.5V
µA VOUT = 5.25V
mA TTL Outputs LOW
mA TTL Outputs HIGH
39 mA TTL Outputs in 3-STATE
Note 10: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under “worst case” conditions.
DIP and PCC TTL-to-ECL AC Electrical Characteristics
VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V
Symbol
Parameter
fMAX
tPLH
tPHL
tPLH
tPHL
tPZH
Toggle Frequency
Tn to En, En
(Transparent)
LE to En, En
OE to En, En
(Cutoff to HIGH)
TC = 0°C
Min Max
180
0.90
2.10
1.40
2.70
2.90
8.00
TC = 25°C
Min Max
180
0.80
2.20
1.50
2.70
2.80
6.90
TC = 85°C
Min Max
180
0.70
2.50
1.80
3.10
2.80
5.80
tPHZ
OE to En, En
(HIGH to Cutoff)
1.30
2.70
1.40
2.90
1.70
3.40
tPHZ
DIR to En, En
(HIGH to Cutoff)
tS Tn to LE
tH Tn to LE
tTLH Transition Time
tTHL 20% to 80%, 80% to 20%
1.30
0.70
0.90
0.45
2.70
1.50
1.40
0.70
0.80
0.45
2.90
1.50
1.80
0.70
0.70
0.45
3.50
1.50
Units
MHz
Conditions
ns Figures 1, 3
ns Figures 1, 3
ns Figures 1, 3
ns Figures 1, 3
ns Figures 1, 3
ns Figures 1, 3
ns Figures 1, 3
ns Figures 1, 3
5 www.fairchildsemi.com
5 Page 
Switching Waveforms (Continued)
Note: OE is HIGH, LE is HIGH
FIGURE 6. ECL-to-TTL Transition, DIR to TTL Output, Disable Time
Applications
FIGURE 7. Applications Diagram—MOS/TTL SRAM Interface Using 100398 ECL–TTL Latched Translator
11 www.fairchildsemi.com
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet 100398QI.PDF ] | |
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